NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
37 / 183
COPT
COPCLKS
2
1
0
Clock
Source
COP
Overflow
Count
COP Overflow Time
(ms, nominal)
1:1
(0.5 MHz)
1:0
(1 MHz)
0:1
(2 MHz)
0:0
(4MHz)
1
0
0
0 Bus Clock
2
13
16.384
8.192
4.096
2.048
1
0
0
1 Bus Clock
2
14
32.768
16.384
8.192
4.096
1
0
1
0 Bus Clock
2
15
65.536
32.768
16.384
8.192
1
0
1
1 Bus Clock
2
16
131.072
65.536
32.768
16.384
1
1
0
0 Bus Clock
2
17
262.144
131.072
65.536
32.768
1
1
0
1 Bus Clock
2
18
524.288
262.144
131.072
65.536
1
1
1
0 Bus Clock
2
19
1048.576 524.288
262.144
131.072
1
1
1
1 Bus Clock
2
19
1048.576 524.288
262.144
131.072
After any reset, the COP timer is enabled. This provides a reliable way to detect code
that is not executing as intended. If the COP watchdog is not used in an application, it
can be disabled by clearing the COPE bit in the write-once SIMOPT1 register. Even if
the application will use the reset default settings in COPE, COPCLKS and COPT[2:0],
the user should still write to write- once SIMOPT1 during reset initialization to lock in the
settings. That way, they cannot be changed accidentally if the application program gets
lost.
The write to SRS that services (clears) the COP timer should not be placed in an
interrupt service routine (ISR) because the ISR could continue to be executed
periodically even if the main application program fails. When the MCU is in ACTIVE
BACKGROUND DEBUG mode, or either Stop1 or Stop4 modes, the COP timer is
temporarily disabled. If enabled, the COP timer is reset at the time entering Stop1 and
Stop4 modes, and will restart after 3 cycles of the selected clock source upon exiting; RTI
may be used as a substitute.
7.4 SIM test register (SIMTST)
The output of the temperature monitor is available using the SIM Test register as shown
in
Table 29
.
Table 29. SIM test register (SIMTST) (address $180F)
Bit
7
6
5
4
3
2
1
0
R
TRO
W
TRH
Reset
0
0
1
1
1
0
0
1
= Reserved
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