NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
36 / 183
modules are disabled and any I/O pins are initially configured as general-purpose high-
impedance inputs with any pullup devices disabled. The I bit in the condition code
register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. The SP is forced to $00FF at
reset. The FXTH87E has seven sources for reset:
•
Power-on reset (POR)
•
Low-voltage detect (LVD)
•
Computer operating properly (COP) timer
•
Periodic hardware reset (PRST)
•
Illegal opcode detect
•
Illegal address detect
•
BACKGROUND DEBUG forced reset
Each of these sources has an associated bit in the system reset status register with the
exception of the BACKGROUND DEBUG forced reset and the periodic hardware reset,
PRST, that is indicated by the PRF bit in the PWUCS1 register.
7.3 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software
fails to execute as expected. To prevent a system reset from the COP timer (when it is
enabled), application software must reset the COP timer periodically. If the application
program gets lost and fails to reset the COP before it times out, a system reset is
generated to force the system back to a known starting point. The COP watchdog is
enabled by the COPE bit in SIMOPT1 register. The COP timer is reset by writing any
value to the address of SRS. This write does not affect the data in the read-only SRS.
Instead, the act of writing to this address is decoded and sends a reset signal to the COP
timer.
The timeout period can be selected by the COPCLKS and the COPT[2:0] bits as shown
in
Table 28
. The COPCLKS bit selects either the LFO or the CPU bus clock as the
clocking source and the COPT[2:0] bits select the clock count required for a timeout. The
tolerances of these timeout periods is dependent on the selected clock source (LFO or
HFO).
Table 28. COP watchdog timeout period
COPT
COPCLKS
2
1
0
Clock
Source
COP
Overflow
Count
COP Overflow Time
(ms, nominal)
0
0
0
0
LFO
2
5
32
0
0
0
1
LFO
2
6
64
0
0
1
0
LFO
2
7
128
0
0
1
1
LFO
2
8
256
0
1
0
0
LFO
2
9
512
0
1
0
1
LFO
2
10
1024
0
1
1
0
LFO
2
11
2048
0
1
1
1
LFO
2
11
2048
BUSCLKS[1:0]
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