NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
110 / 183
13.4 PWU control/status register 1 — PWUCS1
The PWUSC1 register contains six bits to select the division of the incoming RCLK clock
period and provide interrupt flag and acknowledge bits as described in
Table 102
.
Table 102. PWU Control/Status register 1 (PWUCS1) (address $003A)
Bit
7
6
5
4
3
2
1
0
R
PRF
0
W
PRFAK
PRST[5:0]
Reset
0
0
1
1
1
1
1
1
= Reserved
Table 103. PWUSC1 register field descriptions
Field
Description
7
PRF
Periodic Reset Flag — The PRF bit indicates when a periodic reset has been generated by the PWU. MCU
writes to this bit have no effect. This bit is cleared by writing a one to the PRFAK bit. This bit is cleared by a
power on reset, but is unaffected by other resets.
0 Periodic reset not generated or previously acknowledged.
1 Periodic reset generated.
6
PRFAK
Acknowledge PRF Interrupt Flag — The PRFAK bit clears the PRF bit if written with a one. Writing a zero to
the PRFAK bit has no effect on the PRF bit. Reading the PRFAK bit returns a zero. Reset has no effect on
this bit.
0 No effect.
1 Clear PRF bit.
5:0
PRST[5:0]
Periodic Reset Time Interval — These control bits select the number of wakeup interrupts that are needed
before the next periodic reset is generated. The decimal count gives a range of periodic reset times from
1 to 63 wakeup interrupts. Depending on the value of the bits for the WDIV[5:0] and WUT[5:0] this time
interval can nominally be from 1 second to 66 minutes with steps from 1 to 63 seconds. Whenever the
PRST[5:0] bits are changed the timeout period is restarted. Writing the same data to the PRST[5:0] bits has
no effect.
Writing zeros to all of the PRST[5:0] bits forces the periodic reset to be disabled if at least one of the
WUT[5:0] bits is set to a one. This assures that there will be at least a wakeup interrupt. However, writing all
zeros to the PRST[5:0] bits is inhibited if all of the WUT[5:0] bits are already cleared to zero. This prevents
disabling both the periodic wakeup and the periodic reset at the same time. See
Table 101
. The PRST[5:0]
bits are preset to a value of 63 by any resets.
13.5 PWU wakeup status register — PWUS
The PWUS register shows the current status of the two PWU counters as described in
Table 102
. The counter contents are captured when the register is read.
Table 104. PWU wakeup status register (PWUS) (address $001F)
Bit
7
6
5
4
3
2
1
0
R
0
W
PSEL
CSTAT
Reset
0
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