NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
50 / 183
Field
Description
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
LVW
).
0 Low-trip point selected (V
LVW
= V
LVDL
)
1 High-trip point selected (V
LVW
= V
LVDH
)
3:0
Reserved
Reserved Bits — These bits are reserved should not be altered by the user. Any read returns a logical zero.
7.11.7 Free-Running Counter (FRC)
For additional information on the FRC, see
Section 12.8 "Free-Running Counter (FRC)"
.
Once enabled, the FRC continues to increment (and subsequently rolls over) in RUN,
STOP4, STOP3, and STOP1 modes, unless halted as defined below.
Table 49. PMCT register (address $180B)
Bit
7
6
5
4
3
2
1
0
R
W
FRC_CLR
FRC_
EN_HALT
FPAGE
Reset
0
—
0
—
—
—
—
0
= Reserved
Table 50. PMCT register field descriptions
Field
Description
7
FRC_CLR
FRC_CLR — Write-only, free-running counter clear control bit
0 No action taken.
1 Clears the counter value, for example, resets to 0x0000 (may also start at 0x0001 due to the inbound
clock incrementing the counter on both rising and falling edges to achieve ~2 kHz from the 1 kHz LFO
source).
5
FRC_
EN_HALT
FRC_EN_HALT— Read/Write, free-running-counter enable(d) / halt(ed) control bit
0 Free-running-counter is halted in place.
1 Free-running-counter is released and begins/continues to increment.
0
FPAGE
FPAGE — Write-only, free-running-counter control access bit
0 Addresses $1808 and $1809 revert to the PMCRSC and PMCSC1 registers and the FRC remains
functioning as last controlled while FPAGE had been 1.
1 PMCT bits 7 and 5 functions as described above, and addresses $1808 and $1809 become the FRC_
TIMER[15:0] result registers holding the 16-bit free-running-counter value.
Table 51. FRC_TIMER register, MSbyte and LSbyte (address $1808 and $1809)
Bit
7
6
5
4
3
2
1
0
R
FRC_TIMER[15:8]
W
Reset
0
0
0
0
0
0
0
0
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