NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
48 / 183
[2]
This bit can be written only one time after reset. Additional writes are ignored.
Table 44. SPMSC1 register field descriptions
Field
Description
7
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect
event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return logic 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVDF = 1
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets
1 Force an MCU reset when LVDF = 1
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-
voltage detect function operates when the MCU is in STOP mode.
0 Low-voltage detect disabled during STOP mode
1 Low-voltage detect enabled during STOP mode
2
LVDE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the
operation of other bits in this register.
0 LVD logic disabled
1 LVD logic enabled
0
Reserved
Reserved Bit — This bit is reserved should not be altered by the user. Any read returns a logical zero. Any
write should be a logical zero.
0
BGBE
Band gap Buffer Enable — The BGBE bit is used to enable an internal buffer for the band gap voltage
reference for use by the ADC module on one of its internal channels.
0 Band gap buffer disabled
1 Band gap buffer enabled
7.11.5 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to configure the STOP mode behavior of the MCU.
Table 45. System power management status and control 2 register (SPMSC2) (address $180A)
Bit
7
6
5
4
3
2
1
0
R
0
0
0
0
0
W
PPDACK
PDC
[1]
0
Power-
on reset
0
0
0
0
0
0
0
0
Any other
reset
0
0
U
U
0
0
0
0
= Reserved
[1]
This bit can be written only one time after reset. Additional writes are ignored.
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