NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
27 / 183
Start
Write to FLASH,
to buffer address, and data
Write command ($25) to FCMD
No
Yes
FPVIO or
FACCERR?
Write 1 to FCBEF
to launch command
and clear FCBEF (2)
1
0
FCCF?
ERROR exit
Done
Note 2: Wait at least four bus
cycles before checking
FCBEF or FCCF.
0
FACCERR?
Clear error
0
FCBEF?
Write to FCDIV (1)
Note 1: Required only once after reset.
aaa-027999
1
1
FLASH BURST
PROGRAM FLOW
No
Yes
New burst command?
Figure 10. FLASH burst program flowchart
6.7.5 Access errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in
FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT
before any command can be processed.
•
Writing to a FLASH address before the internal FLASH clock frequency has been set
by writing to the FCDIV register
•
Writing to a FLASH address while FCBEF is not set (A new command cannot be
started until the command buffer is empty.)
•
Writing a second time to a FLASH address before launching the previous command
(There is only one write to FLASH for every command.)
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