NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
132 / 183
Field
Description
0
DEQEN
DeQing System enable — The bit controls the DeQing system.
0 DeQing disabled.
1 DeQing enabled.
14.17.10 LFR control register B (LFCTRLB, LPAGE = 1)
The LFCTRLB register contains control bits for the LF detector and decoder. It is only
accessible when the LPAGE bit is set.
Table 127. LFR control register B (LFCTRLB, LPAGE = 1) (address $0024)
Bit
7
6
5
4
3
2
1
0
R
W
HYST[1:0]
LFFAF
LFCAF
LFPOL
LCPTAZ[2:0]
Reset
1
1
0
0
0
1
0
0
Table 128. LFCTRLB register field descriptions
Field
Description
7-6
HYST[1:0]
Control slicer hysteresis
00 20 mV hysteresis
01 40 mV hysteresis
10 50 mV hysteresis
11 30 mV hysteresis — recommended setting
5-4
LFFAF;
LFCAF
Average filter bi-phase filtering control — Activates bi-phase filtering and control offset value
00 Standard low pass filtering activated — recommended setting
01 Standard low pass filtering activated
10 Bi-phase filtering activated — Low offset from input signal low level
11 Bi-phase filtering activated — High offset from input signal low level
3
LFPOL
LF Manchester Polarity Select — This read/write bit selects the polarity of the transition in the middle of the
bit time. The LFPOL is not used in Carrier mode. Reset clears LFPOL bit.
0 Zero is falling edge in middle of a bit time, one is a rising edge in the middle of bit time.
1 Zero is rising edge in middle of a bit time, one is a falling edge in the middle of bit time.
2-0
LFCPT
AZ[2:0]
LF auto-zero counter — Applications to set these bits to 0x06 for proper LF operation. These bits tune the
minimum number of data edges between two auto-zero requests during a data frame.
14.17.11 LFR control register A (LFCTRLA, LPAGE = 1)
The LFCTRLA register contains control bits for the LF detector and factory test selects. It
is only accessible when the LPAGE bit is set.
Table 129. LFR control register A (LFCTRLA, LPAGE = 1) (address $0025)
Bit
7
6
5
4
3
2
1
0
R
W
LFCC[3:0]
Reset
0
0
0
0
0
0
0
0
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