NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
19 / 183
Direct page registers are located within the first 256 locations in the memory map, so
they are accessible with efficient direct addressing mode instructions, which requires
only the lower byte of the address. Bit manipulation instructions can be used to access
any bit in any direct-page register.
Table 7
is a summary of all user-accessible direct-
page registers and control bits. Those related to the TPMS application and modules are
described in detail in this specification.
Table 7. MCU direct page register summary
Cells that are not associated with named bits are shaded
•
Shaded cell with a 0 indicate an unused bit that always reads as 0
•
Shaded cells not containing a value indicate unused or reserved bit locations that could read as 1s or 0s
Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0000
PTAD
PTAD[4:0]
$0001
PTAPE
PTAPE[3:0]
$0002
Reserved
$0003
PTADD
PTADD[3:0]
$0004
PTBD
PTBD[1:0]
$0005
PTBPE
PTBPE[1:0]
$0006
Reserved
$0007
PTBDD
PTBDD[1:0]
$0008
Reserved
$0009
Reserved
$000A
Reserved
$000B
Reserved
$000C
KBISC
0
0
0
0
KBF
KBACK
KBIE
KBIMOD
$000D
KBIPE
KBIPE[3:0]
$000E
KBIES
KBEDG[3:0]
$000F
Reserved
$0010
TPM1SC
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
$0011
TPM1CNTH
Bit [15:8]
$0012
TPM1CNTL
Bit [7:0]
$0013
TPM1MODH
Bit [15:8]
$0014
TPM1MODL
Bit [7:0]
$0015
TPM1C0SC
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
0
0
$0016
TPM1C0VH
Bit [15:8]
$0017
TPM1C0VL
Bit [7:0]
$0018
TPM1C1SC
CH1F
CH1IE
MS1B
MS1A
ELS1B
ELS1A
0
0
$0019
TPM1C1VH
Bit [15:8]
$001A
TPM1C1VL
Bit [7:0]
$001B
Reserved
$001C
PWUDIV
WDIV[5:0]
$001D
PWUCS0
WUF
WUFAK
WUT[5:0]
$001E
PWUCS1
PRF
PRFAK
PRST[5:0]
$001F
PWUS
PSEL
0
CSTAT[5:0]
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