NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
47 / 183
7.11.3 System Operation Register 2 (SIMOPT2)
The following clock source and frequency selections are available using the system
option register 2 as shown in
Table 41
.
Table 41. System option register 2 (SIMOPT2) (address $1803)
Bit
7
6
5
4
3
2
1
0
R
W
COPT[2:0]
LFOSEL
TCLKDIV
BUSCLKS[1:0]
Reset
0
1
1
1
0
0
0
0
= Reserved
Table 42. SIMOPT2 register field descriptions
Field
Description
7
Reserved
Reserved
6:4
COPT[2:0]
COP Watchdog Time Out — These control bits select the timeout period for the COP watchdog timer
as given in
Table 28
. These bits are set by an MCU reset to select the longest watchdog timeout
period. These bits are write-once after power up.
3
LFOSEL
TPM1 Channel 0 Clock Source — This bit determines which signal is connected to the TPM1 Channel
0, see
Section 11 "Timer Pulse-Width Module"
.
0 Select clock input driven by PTA2.
1 Select clock input driven by the LFO.
2
TCLKDIV
TPM1 Channel 0 Clock Source Divider — The divider for the clock source for TPM1 Channel 0, see
Section 11 "Timer Pulse-Width Module"
.
0 Select RFM Dx clock source divided by 1.
1 Select RFM Dx clock source divided by 8.
1:0
BUSCLKS[1:0]
Bus Clock Select — Bus clock frequency selection by changing HFO FLL ratio as shown in
Figure 2
.
The bus clock frequency is always the HFO frequency divided by two. These bits are cleared by a
reset and can be written at any time.
00 Bus Frequency = 4 MHz (HFO = 8 MHz)
01 Bus Frequency = 2 MHz (HFO = 4 MHz)
10 Bus Frequency = 1 MHz (HFO = 2 MHz)
11 Bus Frequency = 0.5 MHz (HFO = 1 MHz)
7.11.4 System Power Management Status and Control 1 Register (SPMSC1)
Table 43. System power management status and control 1 register (SPMSC1) (address $1809)
Bit
7
6
5
4
3
2
1
[1]
0
R
LVDF
0
W
LVDACK
LVDIE
LVDRE
[2]
LVDSE
LVDE
[2]
0
BGBE
Reset
0
0
0
1
1
1
0
0
= Reserved
[1]
Bit 1 is a reserved bit that must always be written to 0.
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
Downloaded from
