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Hitachi H8S/2627, Hardware Manual

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Rev. 1.0, 09/02, page 55 of 568 

 

4.3 Reset 

A reset has the highest exception priority. 

When the 

RES

 pin goes low, all processing halts and this LSI enters the reset state. To ensure that 

this LSI is reset, hold the 

RES

 pin low for at least 20 ms at power-up. To reset the chip during 

operation, hold the 

RES

 pin low for at least 20 states. A reset initializes the internal state of the 

CPU and the registers of on-chip peripheral modules.  

The chip can also be reset by overflow of the watchdog timer. For details, see section 13, 
Watchdog Timer. 

The interrupt control mode is 0 immediately after reset. 

4.3.1 

Reset Exception Handling 

When the 

RES

 pin goes high after being held low for the necessary period, this LSI starts reset 

exception handling as follows:  

1.  The internal state of the CPU and the registers of the on-chip peripheral modules are 

initialized, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1. 

2.

 

The reset exception handling vector address is read and transferred to the PC, and program 
execution starts from the address indicated by the PC. 

 

Figures 4.1 and 4.2 show examples of the reset sequence. 

Summary of Contents for H8S/2627

Page 1: ...etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute a...

Page 2: ...bed here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corporation by various means including the Renesas Technology Corporation Semiconductor home page http www renesas com 4 W...

Page 3: ...Hitachi 16 bit Single Chip Microcomputer H8S 2628 Series H8S 2628 HD64F2628 HD6432628 H8S 2627 HD6432627 Hardware Manual ADE 602 278 Rev 1 0 09 13 02 Hitachi Ltd ...

Page 4: ...e or cause risk of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other char...

Page 5: ...lization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of pr...

Page 6: ...items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given as required as the final part of each section 7 List of Registers 8 Electrical Characteristics 9 Appendix 10 Main Revisions and Additions...

Page 7: ...icable to application devices with specifications that will most probably change Note F ZTAT TM is a trademark of Hitachi Ltd Target Users This manual was written for users who will be using the H8S 2628 Series in the design of application systems Target users are expected to understand the fundamentals of electrical circuits logical circuits and microcomputers Objective This manual was written to...

Page 8: ...our web site Please ensure you have the latest versions of all documents you require http www hitachisemiconductor com H8S 2628 Series manuals Manual Title ADE No H8S 2628 Series Hardware Manual This manual H8S 2600 Series H8S 2000 Series Programming Manual ADE 602 083 User s manuals for development tools Manual Title ADE No H8S H8 300 Series C C Compiler Assembler Optimizing Linkage Editor User s...

Page 9: ...ply Accumulate Register MAC 21 2 4 6 Initial Values of CPU Registers 21 2 5 Data Formats 22 2 5 1 General Register Data Formats 22 2 5 2 Memory Data Formats 24 2 6 Instruction Set 25 2 6 1 Table of Instructions Classified by Function 26 2 6 2 Basic Instruction Formats 36 2 7 Addressing Modes and Effective Address Calculation 38 2 7 1 Register Direct Rn 38 2 7 2 Register Indirect ERn 38 2 7 3 Regis...

Page 10: ...ease 57 4 4 Traces 58 4 5 Interrupts 58 4 6 Trap Instruction 59 4 7 Stack Status after Exception Handling 60 4 8 Usage Note 61 Section 5 Interrupt Controller 63 5 1 Features 63 5 2 Input Output Pins 65 5 3 Register Descriptions 65 5 3 1 Interrupt Priority Registers A to M IPRA to IPRM 66 5 3 2 IRQ Enable Register IER 67 5 3 3 IRQ Sense Control Registers H and L ISCRH ISCRL 68 5 3 4 IRQ Status Regi...

Page 11: ...ne State 90 6 4 Usage Notes 91 6 4 1 Module Stop Mode Setting 91 6 4 2 PC Break Interrupts 91 6 4 3 CMFA and CMFB 91 6 4 4 PC Break Interrupt when DTC Is Bus Master 91 6 4 5 PC Break Set for Instruction Fetch at Address Following BSR JSR JMP TRAPA RTE or RTS Instruction 91 6 4 6 I Bit Set by LDC ANDC ORC or XORC Instruction 91 6 4 7 PC Break Set for Instruction Fetch at Address Following Bcc Instr...

Page 12: ...5 6 Operation Timing 113 8 5 7 Number of DTC Execution States 114 8 6 Procedures for Using DTC 116 8 6 1 Activation by Interrupt 116 8 6 2 Activation by Software 116 8 7 Examples of Use of the DTC 116 8 7 1 Normal Mode 116 8 7 2 Chain Transfer 117 8 7 3 Software Activation 118 8 8 Usage Notes 118 8 8 1 Module Stop Mode Setting 118 8 8 2 On Chip RAM 119 8 8 3 DTCE Bit Setting 119 Section 9 I O Port...

Page 13: ...TB 143 9 7 4 Port B Pull Up MOS Control Register PBPCR 144 9 7 5 Port B Open Drain Control Register PBODR 144 9 7 6 Pin Functions 145 9 8 Port C 146 9 8 1 Port C Data Direction Register PCDDR 147 9 8 2 Port C Data Register PCDR 147 9 8 3 Port C Register PORTC 148 9 8 4 Port C Pull Up MOS Control Register PCPCR 148 9 8 5 Port C Open Drain Control Register PCODR 148 9 8 6 Pin Functions 149 9 9 Port ...

Page 14: ...ion Timing 224 10 8 1 Input Output Timing 224 10 8 2 Interrupt Signal Timing 228 10 9 Usage Notes 231 10 9 1 Module Stop Mode Setting 231 10 9 2 Input Clock Restrictions 231 10 9 3 Caution on Period Setting 231 10 9 4 Conflict between TCNT Write and Clear Operations 232 10 9 5 Conflict between TCNT Write and Increment Operations 233 10 9 6 Conflict between TGR Write and Compare Match 234 10 9 7 Co...

Page 15: ...7 Interrupt Sources 256 11 7 1 Interrupt Sources and DTC Activation 256 11 7 2 A D Converter Activation 257 11 8 Usage Notes 258 11 8 1 Conflict between TCNT Write and Clear 258 11 8 2 Conflict between TCNT Write and Increment 258 11 8 3 Conflict between TCOR Write and Compare Match 259 11 8 4 Conflict between Compare Matches A and B 260 11 8 5 Switching of Internal Clocks and TCNT Operation 260 1...

Page 16: ... 3 1 Watchdog Timer Mode Operation 287 13 3 2 Interval Timer Mode 287 13 4 Interrupts 288 13 5 Usage Notes 288 13 5 1 Notes on Register Access 288 13 5 2 Conflict between Timer Counter TCNT Write and Increment 289 13 5 3 Changing Value of CKS2 to CKS0 290 13 5 4 Switching between Watchdog Timer Mode and Interval Timer Mode 290 13 5 5 Internal Reset in Watchdog Timer Mode 290 13 5 6 OVF Flag Cleari...

Page 17: ...ce 340 14 7 1 Pin Connection Example 340 14 7 2 Data Format Except for Block Transfer Mode 341 14 7 3 Block Transfer Mode 342 14 7 4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode 343 14 7 5 Initialization 344 14 7 6 Data Transmission Except for Block Transfer Mode 344 14 7 7 Serial Data Reception Except for Block Transfer Mode 348 14 7 8 Clock Output Control 349 14...

Page 18: ...ntrol MC0 to MC15 380 15 3 19 Message Data MD0 to MD15 382 15 3 20 HCAN Monitor Register HCANMON 382 15 4 Operation 384 15 4 1 Hardware and Software Resets 384 15 4 2 Initialization after Hardware Reset 384 15 4 3 Message Transmission 390 15 4 4 Message Reception 393 15 4 5 HCAN Sleep Mode 396 15 4 6 HCAN Halt Mode 399 15 5 Interrupt Sources 400 15 6 DTC Interface 401 15 7 CAN Bus Interface 402 15...

Page 19: ...ests 425 16 6 Usage Note 426 16 6 1 Setting of Module Stop Mode 426 Section 17 A D Converter 427 17 1 Features 427 17 2 Input Output Pins 429 17 3 Register Description 430 17 3 1 A D Data Registers A to D ADDRA to ADDRD 430 17 3 2 A D Control Status Register ADCSR 431 17 3 3 A D Control Register ADCR 433 17 4 Operation 434 17 4 1 Single Mode 434 17 4 2 Scan Mode 434 17 4 3 Input Sampling and A D C...

Page 20: ...dling when Programming Erasing Flash Memory 463 19 9 Program Erase Protection 465 19 9 1 Hardware Protection 465 19 9 2 Software Protection 465 19 9 3 Error Protection 465 19 10 Programmer Mode 466 19 11 Power Down States for Flash Memory 466 Section 20 Clock Pulse Generator 467 20 1 Register Descriptions 468 20 1 1 System Clock Control Register SCKCR 468 20 1 2 Low Power Control Register LPWRCR 4...

Page 21: ... Clock Output Disabling Function 490 21 8 Usage Notes 490 21 8 1 I O Port Status 490 21 8 2 Current Consumption during Oscillation Stabilization Wait Period 490 21 8 3 DTC Module Stop 490 21 8 4 On Chip Peripheral Module Interrupt 490 21 8 5 Writing to MSTPCR 491 Section 22 List of Registers 493 22 1 Register Addresses Address Order 494 22 2 Register Bits 510 22 3 Register States in Each Operating...

Page 22: ...Rev 1 0 09 02 page xx of xxxvi Index 565 ...

Page 23: ... Figure 2 13 State Transitions 45 Section 3 MCU Operating Modes Figure 3 1 Address Map 51 Section 4 Exception Handling Figure 4 1 Reset Sequence Advanced Mode with On chip ROM Enabled 56 Figure 4 2 Reset Sequence Advanced Mode with On chip ROM Disabled Not Available in this LSI 57 Figure 4 3 Stack Status after Exception Handling 60 Figure 4 4 Operation when SP Value Is Odd 61 Section 5 Interrupt C...

Page 24: ...xample of Chain Transfer 114 Section 10 16 Bit Timer Pulse Unit TPU Figure 10 1 Block Diagram of TPU 162 Figure 10 2 Example of Counter Operation Setting Procedure 197 Figure 10 3 Free Running Counter Operation 198 Figure 10 4 Periodic Counter Operation 199 Figure 10 5 Example of Setting Procedure for Waveform Output by Compare Match 199 Figure 10 6 Example of 0 Output 1 Output Operation 200 Figur...

Page 25: ... 40 TCIV Interrupt Setting Timing 229 Figure 10 41 TCIU Interrupt Setting Timing 229 Figure 10 42 Timing for Status Flag Clearing by CPU 230 Figure 10 43 Timing for Status Flag Clearing by DTC Activation 230 Figure 10 44 Phase Difference Overlap and Pulse Width in Phase Counting Mode 231 Figure 10 45 Conflict between TCNT Write and Clear Operations 232 Figure 10 46 Conflict between TCNT Write and ...

Page 26: ...83 Figure 13 2 Example of WDT0 Watchdog Timer Operation 287 Figure 13 3 Writing to TCNT TCSR and RSTCSR example for WDT0 289 Figure 13 4 Conflict between TCNT Write and Increment 289 Section 14 Serial Communication Interface SCI Figure 14 1 Block Diagram of SCI 292 Figure 14 2 Data Format in Asynchronous Communication Example with 8 Bit Data Parity Two Stop Bits 315 Figure 14 3 Receive Data Sampli...

Page 27: ...ansfer Rate 343 Figure 14 26 Retransfer Operation in SCI Transmit Mode 345 Figure 14 27 TEND Flag Generation Timing in Transmission Operation 346 Figure 14 28 Example of Transmission Processing Flow 347 Figure 14 29 Retransfer Operation in SCI Receive Mode 348 Figure 14 30 Example of Reception Processing Flow 349 Figure 14 31 Timing for Fixing Clock Output Level 349 Figure 14 32 Clock Halt and Res...

Page 28: ...n Accuracy Definitions 439 Figure 17 6 Example of Analog Input Circuit 440 Figure 17 7 Example of Analog Input Protection Circuit 442 Figure 17 8 Analog Input Pin Equivalent Circuit 442 Section 19 ROM Figure 19 1 Block Diagram of Flash Memory 446 Figure 19 2 Flash Memory State Transitions 447 Figure 19 3 Boot Mode 448 Figure 19 4 User Program Mode 449 Figure 19 5 Flash Memory Block Configuration 4...

Page 29: ...ure 23 4 Reset Input Timing 551 Figure 23 5 Interrupt Input Timing 551 Figure 23 6 I O Port Input Output Timing 555 Figure 23 7 Realtime Input Port Data Input Timing 555 Figure 23 8 TPU Input Output Timing 555 Figure 23 9 TPU Clock Input Timing 556 Figure 23 10 SCK Clock Input Timing 556 Figure 23 11 SCI Input Output Timing Clocked Synchronous Mode 556 Figure 23 12 A D Converter External Trigger I...

Page 30: ...Rev 1 0 09 02 page xxviii of xxxiv ...

Page 31: ...xception Handling Table 4 1 Exception Types and Priority 53 Table 4 2 Exception Handling Vector Table 54 Table 4 3 Statuses of CCR and EXR after Trace Exception Handling 58 Table 4 4 Statuses of CCR and EXR after Trap Instruction Exception Handling 59 Section 5 Interrupt Controller Table 5 1 Pin Configuration 65 Table 5 2 Interrupt Sources Vector Addresses and Interrupt Priorities 73 Table 5 3 Int...

Page 32: ...9 18 P77 Pin Function 135 Table 9 19 P76 Pin Function 135 Table 9 20 P75 Pin Function 135 Table 9 21 P74 Pin Function 135 Table 9 22 P73 Pin Function 136 Table 9 23 P72 Pin Function 136 Table 9 24 P71 Pin Function 136 Table 9 25 P70 Pin Function 136 Table 9 26 PA3 Pin Function 141 Table 9 27 PA2 Pin Function 141 Table 9 28 PA1 Pin Function 141 Table 9 29 PA0 Pin Function 141 Table 9 30 PB7 Pin Fun...

Page 33: ... 7 TPSC0 to TPSC2 Channels 2 169 Table 10 8 TPSC0 to TPSC2 Channel 3 169 Table 10 9 TPSC0 to TPSC2 Channel 4 170 Table 10 10 TPSC0 to TPSC2 Channel 5 170 Table 10 11 MD0 to MD3 172 Table 10 12 TIORH_0 Channel 0 174 Table 10 13 TIORL_0 Channel 0 175 Table 10 14 TIOR_1 Channel 1 176 Table 10 15 TIOR_2 Channel 2 177 Table 10 16 TIORH_3 Channel 3 178 Table 10 17 TIORL_3 Channel 3 179 Table 10 18 TIOR_...

Page 34: ...ting in BRR and Bit Rate B 308 Table 14 3 BRR Settings for Various Bit Rates Asynchronous Mode 1 309 Table 14 3 BRR Settings for Various Bit Rates Asynchronous Mode 2 310 Table 14 3 BRR Settings for Various Bit Rates Asynchronous Mode 3 311 Table 14 4 Maximum Bit Rate for Each Frequency Asynchronous Mode 311 Table 14 5 Maximum Bit Rate with External Clock Input Asynchronous Mode 312 Table 14 6 BRR...

Page 35: ...le 19 5 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible 457 Table 19 6 Flash Memory Operating States 466 Section 20 Clock Pulse Generator Table 20 1 Damping Resistance Value 470 Table 20 2 Crystal Resonator Characteristics 470 Table 20 3 External Clock Input Conditions 472 Section 21 Power Down Modes Table 21 1 Low Power Consumption Mode Transition Conditions 47...

Page 36: ...Rev 1 0 09 02 page xxxiv of xxxiv Table 23 9 Flash Memory Characteristics 561 ...

Page 37: ...ulse generator PPG Watchdog timer Asynchronous or clocked synchronous serial communication interface SCI Hitachi controller area network HCAN Synchronous serial communication unit SSU 10 bit A D converter Clock pulse generator On chip memory ROM Model ROM RAM Remarks F ZTAT Version HD64F2628 128 kbytes 8 kbytes HD6432628 128 kbytes 8 kbytes Under development Masked ROM Version HD6432627 96 kbytes ...

Page 38: ...11 PO9 TIOCB0 P10 PO8 TIOCA0 PF7 φ PF6 PF5 PF4 PF3 PF2 PF1 PF0 RAM Interrupt controller PC break controller 2 channels ROM Masked ROM flash memory TPU PPG Port 1 Port 4 Note The FWE pin is provided only in the flash memory version The NC pin is provided only in the masked ROM version MD2 MD1 MD0 EXTAL XTAL PLLCAP PLLVSS FWE NC NMI H8S 2600 CPU DTC WDT 1 channel TMR 4 channels SCI 3 channels SSU 2 ...

Page 39: ...SS VSS EXTAL XTAL VCC NMI VCL VSS MD2 MD1 MD0 P30 TxD0 P31 RxD0 75747372717069686766656463626160595857565554535251 P32 SCK0 P33 P34 P35 P36 P37 PA3 SCK2 PA2 RxD2 PA0 PB7 TIOCB5 PB5 TIOCB4 PB4 TIOCA4 PB3 TIOCD3 PB2 TIOCC3 VSS PB1 TIOCB3 VCC PB0 TIOCA3 PC7 PC6 SSCK1 PC5 SSI1 PC4 SSO1 PC3 PA1 TxD2 PB6 TIOCA5 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 P16 PO14 TIOCA2 VCC P17 PO15 TIOCB2 TCLKD ...

Page 40: ...tal resonator For examples of crystal resonator connection and external clock input see section 20 Clock Pulse Generator EXTAL 63 Input For connection to a crystal resonator An external clock can be supplied from the EXTAL pin For examples of crystal resonator connection and external clock input see section 20 Clock Pulse Generator φ 68 Output Supplies the system clock to external devices Operatin...

Page 41: ...t compare output PWM output pins TIOCA2 TIOCB2 1 3 Input Output TGRA_2 to TGRB_2 input capture input output compare output PWM output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 31 33 35 36 Input Output TGRA_3 to TGRD_3 input capture input output compare output PWM output pins TIOCA4 TIOCB4 37 38 Input Output TGRA_4 to TGRB_4 input capture input output compare output PWM output pins TIOCA5 TIOCB5 39 40 Input...

Page 42: ... Input Output Data input output pins SSCK1 SSCK0 29 25 Input Output Clock input output pins Synchro nous serial communi cation unit SSU SCS1 SCS0 30 26 Input Output Chip select input output pins A D converter AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 76 77 78 79 80 81 82 83 87 88 89 90 91 92 93 94 Input Analog input pins ADTRG 72 Input Pin for input of an external trigg...

Page 43: ...s P17 P16 P15 P14 P13 P12 P11 P10 3 1 100 99 98 97 96 95 Input Output Eight input output pins P37 P36 P35 P34 P33 P32 P31 P30 45 46 47 48 49 50 51 52 Input Output Eight input output pins P47 P46 P45 P44 P43 P42 P41 P40 87 88 89 90 91 92 93 94 Input Eight input pins P77 P76 P75 P74 P73 P72 P71 P70 14 13 12 11 10 9 8 7 Input Output Eight input output pins P97 P96 P95 P94 P93 P92 P91 P90 76 77 78 79 ...

Page 44: ...3 PB2 PB1 PB0 40 39 38 37 36 35 33 31 Input Output Eight input output pins PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 30 29 28 27 26 25 24 23 Input Output Eight input output pins PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 22 21 20 19 18 17 16 15 Input Output Eight input output pins PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 68 69 70 71 72 73 74 75 Input Output Eight input output pins ...

Page 45: ...eight 32 bit registers Sixty nine basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Multiply and accumulate instruction Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 32 ERn Register indirect with post increment or pre decrement ERn or ERn Absolu...

Page 46: ...are shown below Register configuration The MAC register is supported by the H8S 2600 CPU only Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported by the H8S 2600 CPU only The number of execution states of the MULXU and MULXS instructions Execution States Instruction Mnemonic H8S 2600 H8S 2000 MULXU MULXU B Rs Rd 3 12 MULXU W Rs ERd 4 20 MULXS MULXS B Rs Rd 4 13 MULXS ...

Page 47: ...d divide instructions have been added A multiply and accumulate instruction has been added Two bit shift instructions have been added Instructions for saving and restoring multiple registers have been added A test and set instruction has been added Higher speed Basic instructions execute twice as fast 2 1 3 Differences from H8 300H CPU In comparison to the H8 300H CPU the H8S 2600 CPU has the foll...

Page 48: ...wer 16 bits of effective addresses EA are valid Exception Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H 0000 is allocated to the exception vector table One branch address is stored per 16 bits The exception vector table structure in normal mode is shown in figure 2 1 For details of the exception vector table see section 4 Exception Handling The memory ...

Page 49: ... PC 16 bits SP SP SP 2 1 When EXR is not used it is not stored on the stack 2 SP when EXR is not used 3 lgnored when returning Notes b Exception Handling a Subroutine Branch Figure 2 2 Stack Structure in Normal Mode 2 2 2 Advanced Mode Address Space Linear access to a 16 Mbyte maximum address space is provided Extended Registers En The extended registers E0 to E7 can be used as 16 bit registers or...

Page 50: ... indirect addressing mode aa 8 employed in the JMP and JSR instructions uses an 8 bit absolute address included in the instruction code to specify a memory operand that contains a branch address In advanced mode the operand is a 32 bit longword operand providing a 32 bit branch address The upper 8 bits of these 32 bits is a reserved area that is regarded as H 00 Branch addresses can be stored in t...

Page 51: ... 1 Reserved 1 3 CCR PC 24 bits SP SP SP 2 Reserved a Subroutine Branch b Exception Handling Notes 1 When EXR is not used it is not stored on the stack 2 SP when EXR is not used 3 Ignored when returning Figure 2 4 Stack Structure in Advanced Mode ...

Page 52: ...ximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product refer to section 3 MCU Operating Modes H 0000 H FFFF H 00000000 H FFFFFFFF H 00FFFFFF 64 kbyte 16 Mbyte Cannot be used in this LSI Program area Data area b Advanced Mode a Normal Mode Figure 2 5 Memory Map Cannot be used for this LSI ...

Page 53: ... 32 41 31 0 0 15 0 7 0 7 0 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply accumulate r...

Page 54: ...are functionally equivalent providing a maximum of sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum of sixteen 8 bit registers The usage of each register can be selected independentl...

Page 55: ...anipulates the LDC STC ANDC ORC and XORC instructions When these instructions except for the STC instruction are executed all interrupts including NMI will be masked for three states after execution is completed Bit Bit Name Initial Value R W Description 7 T 0 R W Trace Bit When this bit is set to 1 a trace exception is generated each time an instruction is executed When this bit is cleared to 0 i...

Page 56: ... be read or written by software using the LDC STC ANDC ORC and XORC instructions This bit cannot be used as an interrupt mask bit in this LSI 5 H undefined R W Half Carry Flag When the ADD B ADDX B SUB B SUBX B CMP B or NEG B instruction is executed this flag is set to 1 if there is a carry or borrow at bit 3 and cleared to 0 otherwise When the ADD W SUB W CMP W or NEG W instruction is executed th...

Page 57: ...ns 2 4 5 Multiply Accumulate Register MAC This 64 bit register stores the results of multiply and accumulate operations It consists of two 32 bit registers denoted MACH and MACL The lower 10 bits of MACH are valid the upper bits are a sign extension 2 4 6 Initial Values of CPU Registers Reset exception handling loads the CPU s program counter PC from the vector table clears the trace bit in EXR to...

Page 58: ... treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats in general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care Don t care Don t care 7 0 4 3 7 0 Don t care 6 5 4 3 2 7 1 0 7 0 Don t care 6 5 4 3 2 7 1 0 Don t care RnH RnL RnH RnL RnH RnL Data Type Register Number Data Format Byte data Byte data 4 bit BCD data 4 bit BCD data 1 ...

Page 59: ...n RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Format Register Number Word data Word data Rn En Longword data Legend ERn Figure 2 9 General Register Data Formats 2 ...

Page 60: ...ror does not occur however the least significant bit of the address is regarded as 0 so access begins the preceding address This also applies to instruction fetches When ER7 is used as an address register to access the stack the operand size should be word or longword 7 0 7 6 5 4 3 2 1 0 MSB LSB MSB MSB LSB LSB Data Type Address 1 bit data Byte data Word data Address L Address L Address 2M Address...

Page 61: ...ic operations AND OR XOR NOT B W L 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Total 69 Notes B byte W word L longword 1 POP W Rn and PUSH W Rn are identical to MOV W SP Rn and...

Page 62: ...ply accumulate register 32 bit register EAd Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical XOR Move NOT logi...

Page 63: ...t be used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP PUSH L ERn is identical to MOV L ERn SP LDM L SP Rn register list Pops two or more general registers from the stack STM L Rn register list SP Pushes two or...

Page 64: ...n be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general registers either 8 b...

Page 65: ... to longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by extending the sign bit TAS 2 B ERd 0 1 bit 7 of ERd Tests memory contents and sets the most significant bit bit 7 to 1 MAC EAs EAd MAC MAC Performs signed multiplication on memory contents and adds...

Page 66: ... data OR B W L Rd Rs Rd Rd IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B W L Rd Rs Rd Rd IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B W L Rd Rd Takes the one s complement logical complement of general register contents Note Refers to the operand size B ...

Page 67: ...le SHLL SHLR B W L Rd shift Rd Performs a logical shift on general register contents 1 bit or 2 bit shifts are possible ROTL ROTR B W L Rd rotate Rd Rotates general register contents 1 bit or 2 bit rotations are possible ROTXL ROTXR B W L Rd rotate Rd Rotates general register contents through the carry flag 1 bit or 2 bit rotations are possible Note Refers to the operand size B Byte W Word L Longw...

Page 68: ...ral register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND B B C bit No of EAd C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C bit No of EAd C ANDs the carry flag with the inverse of a specified bit i...

Page 69: ... by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BST BIST B B C bit No of EAd Transfers the carry flag value to a specified bit in a general reg...

Page 70: ... High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified addres...

Page 71: ...n them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size transfers are performed between them and memory The upper 8 bits are valid ANDC B CCR IMM CCR EXR IMM EXR Logically ANDs the CCR or EXR contents with immediate data ORC B CCR IMM CCR EXR IMM EXR Logically ORs the CCR o...

Page 72: ... address set in ER5 transfers data for the number of bytes set in R4L or R4 to the address location set in ER6 Execution of the next instruction begins as soon as the transfer is completed 2 6 2 Basic Instruction Formats The H8S 2600 CPU instructions consist of 2 byte 1 word units An instruction consists of an operation field op field a register field r field an effective address extension EA fiel...

Page 73: ... 4 bits Some instructions have two register fields Some have no register field Effective Address Extension 8 16 or 32 bits specifying immediate data an absolute address or a displacement Condition Field Specifies the branching condition of Bcc instructions op op rn rm NOP RTS etc ADD B Rn Rm etc MOV B d 16 Rn Rm etc rn rm op EA disp op cc EA disp BRA d 16 etc 1 Operation field only 2 Operation fie...

Page 74: ...ndirect with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 aa 32 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 2 7 1 Register Direct Rn The register field of the instruction specifies an 8 16 or 32 bit general register containing the operand R0H to R7H and R0L to R7L can be specified as 8 bit registers R0 to R7 and E0 to E7 can be specifi...

Page 75: ...truction For the word or longword transfer instructions the register value should be even 2 7 5 Absolute Address aa 8 aa 16 aa 24 or aa 32 The instruction code contains the absolute address of a memory operand The absolute address may be 8 bits long aa 8 16 bits long aa 16 24 bits long aa 24 or 32 bits long aa 32 Table 2 12 indicates the accessible absolute address ranges To access data the absolu...

Page 76: ...66 to 32768 bytes 16383 to 16384 words from the branch instruction The resulting value should be an even number 2 7 8 Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The instruction code contains an 8 bit absolute address specifying a memory operand This memory operand contains a branch address The upper bits of the absolute address are all assumed to be 0 so the address...

Page 77: ...available in this LSI Figure 2 12 Branch Address Specification in Memory Indirect Mode 2 7 9 Effective Address Calculation Table 2 13 indicates how effective addresses are calculated in each addressing mode In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16 bit address Note Normal mode is not available in this LSI ...

Page 78: ...on t care 24 24 24 24 Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA Register direct Rn General register contents General register contents General register contents General register contents Sign extension Register indirect ERn Register indirect with post increment or pre decrement Register indirect with post increment ERn Register indirect with pre decr...

Page 79: ...on Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relative d 8 PC d 16 PC Memory indirect aa 8 Normal mode Advanced mode 31 0 Don t care 23 0 disp 0 31 23 31 0 Don t care disp op 23 op 8 abs 31 0 abs H 000000 7 8 0 15 31 23 31 0 Don t care 15 H 00 16 op abs 31 0 abs H 000000 7 8 0 31 24 24 24 Not...

Page 80: ... overflow Exception Handling State The exception handling state is a transient state that occurs when the CPU alters the normal processing flow due to an exception source such as a reset trace interrupt or trap instruction The CPU fetches a start address vector from the exception vector table and branches to that address For further details refer to section 4 Exception Handling Program Execution S...

Page 81: ...he watchdog timer overflows Bus request End of bus request Request for exception handling End of exception handling Figure 2 13 State Transitions 2 9 Usage Note 2 9 1 Notes on Using the Bit Operation Instruction Instructions BSET BCLR BNOT BST and BIST read data in byte units and write data in byte units after bit operation Therefore attention must be paid when these instructions are used for port...

Page 82: ...Rev 1 0 09 02 page 46 of 568 ...

Page 83: ... this LSI Therefore all mode pins must be fixed high as shown in table 3 1 Do not change the mode pin settings during operation Table 3 1 MCU Operating Mode Selection MCU CPU External Data Bus Operating Mode MD2 MD1 MD0 Operating Mode Description On Chip ROM Initial Width Max Width 7 1 1 1 Advanced mode Single chip mode Enabled 3 2 Register Descriptions The following registers are related to the o...

Page 84: ...and cannot be modified 2 1 0 MDS2 MDS1 MDS0 R R R Mode select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 the current operating mode Bits MDS2 to MDS0 correspond to MD2 to MD0 MDS2 to MDS0 are read only bits and they cannot be written to The mode pin MD2 to MD0 input levels are latched into these bits when MDCR is read These latches are canceled by a reset These latches are canc...

Page 85: ... read as 0 and cannot be modified 5 4 INTM1 INTM0 0 0 R W R W These bits select the control mode of the interrupt controller For details of the interrupt control modes see section 5 6 Interrupt Control Modes and Interrupt Operation 00 Interrupt control mode 0 01 Setting prohibited 10 Interrupt control mode 2 11 Setting prohibited 3 NMIEG 0 R W NMI Edge Select Selects the valid edge of the NMI inte...

Page 86: ... 3 Pin Functions in Each Operating Mode The CPU can access a 16 Mbyte address space in advanced mode The on chip ROM is enabled however external addresses cannot be accessed All I O ports are available for use as input output ports ...

Page 87: ...T masked ROM On chip RAM On chip RAM Internal I O registers Internal I O registers ROM 128 kbytes RAM 8 kbytes Mode 7 Advanced single chip mode H 000000 H 017FFF H FFD800 H FFEFBF H FFF800 H FFFFC0 H FFFFFF H FFFF3F H FFFF60 H FFFFBF H8S 2627 On chip ROM Masked ROM On chip RAM On chip RAM Internal I O registers Internal I O registers ROM 96 kbytes RAM 6 kbytes Mode 7 Advanced single chip mode Figu...

Page 88: ...Rev 1 0 09 02 page 52 of 568 ...

Page 89: ...on or exception handling ends if the trace T bit in EXR is set to 1 Direct transition Starts when a direction transition occurs as the result of SLEEP instruction execution Interrupt Starts when execution of the current instruction or exception handling ends if an interrupt request has been issued 2 Low Trap instruction 3 Started by execution of a trap instruction TRAPA Notes 1 Traces are enabled ...

Page 90: ...0028 to H 002B 3 11 H 0016 to H 0017 H 002C to H 002F Reserved for system use 12 H 0018 to H 0019 H 0030 to H 0033 13 H 001A to H 001B H 0034 to H 0037 14 H 001C to H 001D H 0038 to H 003B 15 H 001E to H 001F H 003C to H 003F External interrupt IRQ0 16 H 0020 to H 0021 H 0040 to H 0043 IRQ1 17 H 0022 to H 0023 H 0044 to H 0047 IRQ2 18 H 0024 to H 0025 H 0048 to H 004B IRQ3 19 H 0026 to H 0027 H 00...

Page 91: ...verflow of the watchdog timer For details see section 13 Watchdog Timer The interrupt control mode is 0 immediately after reset 4 3 1 Reset Exception Handling When the RES pin goes high after being held low for the necessary period this LSI starts reset exception handling as follows 1 The internal state of the CPU and the registers of the on chip peripheral modules are initialized the T bit in EXR...

Page 92: ...g vector address when reset 1 H 000000 3 H 000002 2 4 Start address contents of reset exception handling vector address 5 Start address 5 2 4 6 First program instruction φ Internal address bus Internal read signal Internal write signal Internal data bus 1 2 4 6 3 5 Figure 4 1 Reset Sequence Advanced Mode with On chip ROM Enabled ...

Page 93: ... the stack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset exception handling is executed Since the first instruction of a program is always executed immediately after the reset make sure that this instruction initializes the stack pointer example MOV L xx 32 ...

Page 94: ...ed even within the trace exception handling routine Table 4 3 Statuses of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used 2 1 0 Legend 1 Set to 1 0 Cleared to 0 Retains value prior to execution 4 5 Interrupts Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control mo...

Page 95: ...he T bit is cleared to 0 3 A vector address corresponding to the interrupt source is generated the start address is loaded from the vector table to the PC and program execution starts from that address The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3 as specified in the instruction code Table 4 4 shows the statuses of CCR and EXR ...

Page 96: ...n handling CCR CCR 1 PC 16 bits SP EXR Reserved 1 CCR CCR 1 PC 16 bits SP CCR PC 24 bits SP EXR Reserved 1 CCR PC 24 bits SP a Normal Modes 2 b Advanced Modes Interrupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 Notes 1 2 Ignored on return Normal modes are not available in this LSI Figure 4 3 Stack Status after Exception Handling ...

Page 97: ... to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 4 shows an example of what happens when the SP value is odd SP CCR PC R1L SP Condition code register Program counter General register R1L Stack pointer CCR SP SP R1L H FFFEFA H FFFEFB H FFFEFC H FFFEFD H FFFEFE H FFFEFF PC PC TRAP instruction executed SP set to H FF...

Page 98: ...Rev 1 0 09 02 page 62 of 568 ...

Page 99: ... interrupts except NMI NMI is assigned the highest priority level of 8 and can be accepted at all times Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine Seven external interrupts NMI is the highest priority interrupt and is accepted at all times Rising edge or falling...

Page 100: ...T_i1 NMIEG INTM1 INTM0 NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU ISCR IER ISR IPR SYSCR IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Legend Figure 5 1 Block Diagram of Interrupt Controller ...

Page 101: ...stem control register SYSCR refer to section 3 2 2 System Control Register SYSCR System control register SYSCR IRQ sense control register H ISCRH IRQ sense control register L ISCRL IRQ enable register IER IRQ status register ISR Interrupt priority register A IPRA Interrupt priority register B IPRB Interrupt priority register C IPRC Interrupt priority register D IPRD Interrupt priority register E I...

Page 102: ...e R W Description 7 0 Reserved These bits are always read as 0 6 5 4 IPR6 IPR5 IPR4 1 1 1 R W R W R W Sets the priority of the corresponding interrupt source 000 Priority level 0 Lowest 001 Priority level 1 010 Priority level 2 011 Priority level 3 100 Priority level 4 101 Priority level 5 110 Priority level 6 111 Priority level 7 Highest 3 0 Reserved These bits are always read as 0 2 1 0 IPR2 IPR...

Page 103: ...E 0 R W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1 4 IRQ4E 0 R W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1 3 IRQ3E 0 R W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1 2 IRQ2E 0 R W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1 1 IRQ1E 0 R W IRQ1 Enable The IRQ1 interrupt request is enabled when this ...

Page 104: ... Sense Control A 00 Interrupt request generated at IRQ5 input level low 01 Interrupt request generated at falling edge of IRQ5 input 10 Interrupt request generated at rising edge of IRQ5 input 11 Interrupt request generated at both falling and rising edges of IRQ5 input 9 8 IRQ4SCB IRQ4SCA 0 0 R W R W IRQ4 Sense Control B IRQ4 Sense Control A 00 Interrupt request generated at IRQ4 input level low ...

Page 105: ...t 10 Interrupt request generated at rising edge of IRQ2 input 11 Interrupt request generated at both falling and rising edges of IRQ2 input 3 2 IRQ1SCB IRQ1SCA 0 0 R W R W IRQ1 Sense Control B IRQ1 Sense Control A 00 Interrupt request generated at IRQ1 input level low 01 Interrupt request generated at falling edge of IRQ1 input 10 Interrupt request generated at rising edge of IRQ1 input 11 Interru...

Page 106: ...0F 0 0 0 0 0 0 R W R W R W R W R W R W Setting conditions When the interrupt source selected by the ISCR registers occurs Clearing conditions Cleared by reading IRQnF flag when IRQnF 1 then writing 0 to IRQnF flag When interrupt exception handling is executed when low level detection is set and IRQn input is high When IRQn interrupt exception handling is executed when falling rising or both edge d...

Page 107: ...t is possible to select whether an interrupt is generated by a low level falling edge rising edge or both edges at pins IRQ0 to IRQ5 Enabling or disabling of interrupt requests IRQ0 to IRQ5 can be selected with IER The interrupt priority level can be set with IPR The status of interrupt requests IRQ0 to IRQ5 is indicated in ISR ISR flags can be cleared to 0 by software The detection of IRQ0 to IRQ...

Page 108: ...troller The interrupt priority level can be set by means of IPR The DTC can be activated by a TPU SCI or other interrupt request When the DTC is activated by an interrupt request it is not affected by the interrupt control mode or CPU interrupt mask bit 5 5 Interrupt Exception Handling Vector Table Table 5 2 shows interrupt exception handling sources vector addresses and interrupt priorities For d...

Page 109: ...0 IRQ5 21 H 0054 Reserved for system use 22 H 0058 Reserved for system use 23 H 005C DTC SWDTEND 24 H 0060 IPRC2 to IPRC0 Watchdog timer 0 WOVI0 25 H 0064 IPRD6 to IPRD4 PC break control PC break 27 H 006C IPRE6 to IPRE4 A D ADI 28 H 0070 IPRE2 to IPRE0 TPU TGIA_0 32 H 0080 IPRF6 to IPRF4 channel 0 TGIB_0 33 H 0084 TGIC_0 34 H 0088 TGID_0 35 H 008C TCIV_0 36 H 0090 TPU TGIA_1 40 H 00A0 IPRF2 to IP...

Page 110: ...7 H 00E4 TCIV_4 58 H 00E8 TCIU_4 59 H 00EC TPU TGIA_5 60 H 00F0 IPRH2 to IPRH0 channel 5 TGIB_5 61 H 00F4 TCIV_5 62 H 00F8 TCIU_5 63 H 00FC CMIA_0 64 H 0100 IPRI6 to IPRI4 8 bit timer channel 0 CMIB_0 65 H 0104 OVI_0 66 H 0108 CMIA_1 68 H 0110 IPRI2 to IPRI0 8 bit timer channel 1 CMIB_1 69 H 0114 OVI_1 70 H 0118 SCI ERI_0 80 H 0140 IPRJ2 to IPRJ0 channel 0 RXI_0 81 H 0144 TXI_0 82 H 0148 TEI_0 83 ...

Page 111: ... timer channel 2 CMIB_2 93 H 0174 OVI_2 94 H 0178 CMIA_3 96 H 0180 8 bit timer channel 3 CMIB_3 97 H 0184 OVI_3 98 H 0188 HCAN ERS0 OVR0 104 H 01A0 IPRM6 to IPRM4 RM0 105 H 01A4 RM1 106 H 01A8 SLE0 107 H 01AC SSEr_i0 108 H 01B0 IPRM2 to IPRM0 SSU channel 0 SSRx_i0 109 H 01B4 SSTx_i0 110 H 01B8 SSU channel 1 SSERT_i1 111 H 01BC Low Note Lower 16 bits of the start address ...

Page 112: ...tion in this case 1 If an interrupt source occurs when the corresponding interrupt enable bit is set to 1 an interrupt request is sent to the interrupt controller 2 If the I bit in CCR is set to 1 only an NMI interrupt is accepted and other interrupt requests are held pending If the I bit is cleared an interrupt request is accepted 3 When interrupt requests are sent to the interrupt controller the...

Page 113: ...rrupt generated NMI IRQ0 IRQ1 SSERT_i1 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 ...

Page 114: ...table 5 2 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher than the mask level set at that time is held pending and only an interrupt request with a priority higher than the interrupt mask level is accepted 4 When the CPU accepts an interrupt request it starts interrupt exception ha...

Page 115: ...nterrupt handling routine Hold pending Level 1 interrupt Mask level 0 Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5 4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 5 6 3 Interrupt Exception Handling Sequence Figure 5 5 shows the interrupt exception handling sequence The example shown is for the case where interrupt control mode 0 is set in advanced mode and the...

Page 116: ...nal read signal Internal write signal Internal data bus φ 3 1 2 4 3 5 7 Instruction prefetch address Not executed This is the contents of the saved PC the return address Instruction code Not executed Instruction prefetch address Not executed SP 2 SP 4 Saved PC and saved CCR Vector address Interrupt handling routine start address Vector address contents Interrupt handling routine start address 13 1...

Page 117: ...errupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 1 Interrupt priority determination 1 3 3 3 3 2 Number of wait states until executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 2 SK 3 SK 4 Vector fetch SI SI 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 2 SI 2 SI 6 Internal processing 4 2 2 2 ...

Page 118: ...e disabling becomes effective after execution of the instruction When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV and if an interrupt is generated during execution of the instruction the interrupt concerned will still be enabled on completion of the instruction and so interrupt exception handling for that interrupt will be executed on completion of the instruction...

Page 119: ...XORC After any of these instructions are executed all interrupts including NMI are disabled and the next instruction is always executed When the I bit is set by one of these instructions the new value becomes valid two states after execution of the instruction ends 5 7 3 When Interrupts Are Disabled There are times when interrupt acceptance is disabled by the interrupt controller The interrupt con...

Page 120: ...ing the transfer is not accepted until the transfer is completed With the EEPMOV W instruction if an interrupt request is issued during the transfer interrupt exception handling starts at a break in the transfer cycle The PC value saved on the stack in this case is the address of the next instruction Therefore if an interrupt is generated during execution of an EEPMOV W instruction the following c...

Page 121: ...6 1 6 1 Features Two break channels A and B 24 bit break address Bit masking possible Four types of break compare conditions Instruction fetch data read data write data read write Bus master Either CPU or CPU DTC can be selected The timing of PC break exception handling after the occurrence of a break condition is as follows Immediately before execution of the instruction fetched at the set addres...

Page 122: ...eak controller has the following registers Break address register A BARA Break address register B BARB Break control register A BCRA Break control register B BCRB 6 2 1 Break Address Register A BARA BARA is a 32 bit readable writable register that specifies the channel A break address Bit Bit Name Initial Value R W Description 31 to 24 Undefined Reserved These bits are read as an undefined value a...

Page 123: ...ddress Mask Register A2 to A0 These bits specify which bits of the break address set in BARA are to be masked 000 BAA23 to BAA0 All bits are unmasked 001 BAA23 to BAA1 Lowest bit is masked 010 BAA23 to BAA2 Lower 2 bits are masked 011 BAA23 to BAA3 Lower 3 bits are masked 100 BAA23 to BAA4 Lower 4 bits are masked 101 BAA23 to BAA8 Lower 8 bits are masked 110 BAA23 to BAA12 Lower 12 bits are masked...

Page 124: ...o 1 to enable break interrupts 3 When the instruction at the set address is fetched a PC break request is generated immediately before execution of the fetched instruction and the condition match flag CMFA is set 4 After priority determination by the interrupt controller PC break interrupt exception handling is started 6 3 2 PC Break Interrupt Due to Data Access 1 Set the break address in BARA For...

Page 125: ...ddress after a SLEEP instruction is shown below When the SLEEP instruction causes a transition from high speed medium speed mode to sleep mode After execution of the SLEEP instruction a transition is not made to sleep mode and PC break exception handling is executed After execution of PC break exception handling the instruction at the address after the SLEEP instruction is executed figure 6 2 A Wh...

Page 126: ...upt by instruction fetch is set and a break interrupt is generated if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below and that address indicates on chip ROM or RAM the instruction will be one state later than in normal operation Addressing modes ERn d 16 ERn d 32 ERn ERn ERn aa 8 aa 24 aa 32 d 8 PC d 16 PC aa 8 When break interrupt by...

Page 127: ...t when DTC Is Bus Master A PC break interrupt generated when the DTC is the bus master is accepted after the bus mastership has been transferred to the CPU by the bus controller 6 4 5 PC Break Set for Instruction Fetch at Address Following BSR JSR JMP TRAPA RTE or RTS Instruction Even if the instruction at the address following a BSR JSR JMP TRAPA RTE or RTS instruction is fetched it is not execut...

Page 128: ...e with the branch condition and is not generated if the instruction at the next address is not executed 6 4 8 PC Break Set for Instruction Fetch at Branch Destination Address of Bcc Instruction A PC break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition and is not generated if the instruction at the branch destination is not ex...

Page 129: ...The period from one rising edge of φ to the next is referred to as a state The memory cycle or bus cycle consists of one two three or four states Different methods are used to access on chip memory and on chip support modules 7 1 1 On Chip Memory Access Timing ROM RAM On chip memory is accessed in one state The data bus is 16 bits wide permitting both byte and word transfer instruction Figure 7 1 ...

Page 130: ...s cycle Address Read data Write data Internal read signal Internal data bus Internal write signal Internal data bus Read Write Figure 7 2 On Chip Support Module Access Cycle 7 1 3 On Chip HCAN Module Access Timing On chip HCAN module access is performed in four states The data bus width is 16 bits Wait states can be inserted by means of a wait request from the HCAN On chip HCAN module access timin...

Page 131: ... master operations There are two bus masters the CPU and DTC which perform read write operations when they control the bus 7 2 1 Order of Priority of the Bus Masters Each bus master requests the bus mastership by means of a bus request signal The bus arbiter detects the bus masters bus request signals and if the bus mastership is requested sends a bus request acknowledge signal to the bus master m...

Page 132: ...us mastership is transferred at a break between bus cycles However if a bus cycle is executed in discrete operations as in the case of a longword size access the bus mastership is not transferred between such operations For details refer to section 2 7 Bus Status in Instruction Execution in the H8S 2600 Series H8S 2000 Series Programming Manual If the CPU is in sleep mode it transfers the bus mast...

Page 133: ...C to the on chip RAM 1 kbyte enabling 32 bit 1 state reading and writing of the DTC register information 8 1 Features Transfer is possible over any number of channels Three transfer modes Normal repeat and block transfer modes are available One activation source can trigger a number of data transfers chain transfer The direct specification of 16 Mbyte address space is possible Activation by softwa...

Page 134: ...terrupt request MRA MRB CRA CRB DAR SAR MRA MRB CRA CRB SAR DAR DTCERA to DTCERG DTVECR DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to G DTC vector register Legend DTC service request Control logic Register information Figure 8 1 Block Diagram of DTC ...

Page 135: ...C transfer count register A CRA DTC transfer count register B CRB These six registers cannot be directly accessed from the CPU When activated the DTC reads a set of register information that is stored in on chip RAM to the corresponding DTC registers and transfers data After the data transfer it writes a set of updated register information back to the RAM DTC enable registers DTCER DTC vector regi...

Page 136: ...r a data transfer 0X DAR is fixed 10 DAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 11 DAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 3 2 MD1 MD0 Undefined Undefined DTC Mode These bits specify the DTC transfer mode 00 Normal mode 01 Repeat mode 10 Block transfer mode 11 Setting prohibited 1 DTS Undefined DTC Transfer Mode Select Specifies whether the source s...

Page 137: ...hese bits 8 2 3 DTC Source Address Register SAR SAR is a 24 bit register that designates the source address of data to be transferred by the DTC For word size transfer specify an even source address 8 2 4 DTC Destination Address Register DAR DAR is a 24 bit register that designates the destination address of data to be transferred by the DTC For word size transfer specify an even destination addre...

Page 138: ...r DTCE bit setting use bit manipulation instructions such as BSET and BCLR for reading and writing If all interrupts are masked multiple activation sources can be set at one time only at the initial setting by writing data after executing a dummy read on the relevant register Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 0 0 0 0 0 0 0 0 ...

Page 139: ... Vectors 0 to 6 These bits specify a vector number for DTC software activation The vector address is expressed as H 0400 vector number 2 For example when DTVEC6 to DTVEC0 H 10 the vector address is H 0420 When the bit SWDTE is 0 these bits can be written 8 3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software An interrupt request can be directed t...

Page 140: ...ters in that order from the start address of the register information In the case of chain transfer register information should be located in consecutive areas and the register information start address should be located at the vector address corresponding to the interrupt source as shown in figure 8 3 The DTC reads the start address of the register information from the vector address set for each...

Page 141: ... DAR CRA CRB MRA SAR MRB DAR CRA CRB Lower address 4 bytes Register information Register information for 2nd transfer in chain transfer Register information start address Chain transfer Figure 8 3 Location of DTC Register Information in Address Space ...

Page 142: ...2A DTCEA2 Reserved for 22 H 042C DTCEA1 System use 23 H 042E DTCEA0 A D counter ADI A D conversion end 28 H 0438 DTCEB6 TPU TGIA_0 32 H 0440 DTCEB5 channel 0 TGIB_0 33 H 0442 DTCEB4 TGIC_0 34 H 0444 DTCEB3 TGID_0 35 H 0446 DTCEB2 TPU TGIA_1 40 H 0450 DTCEB1 channel 1 TGIB_1 41 H 0452 DTCEB0 TPU TGIA_2 44 H 0458 DTCEC7 channel 2 TGIB_2 45 H 045A DTCEC6 TPU TGIA_3 48 H 0460 DTCEC5 channel 3 TGIB_3 4...

Page 143: ...5 H 04D2 DTCEG6 Reserved for system use 106 H 04D4 DTCEG5 Reserved for system use 107 H 04D6 DTCEG4 SSU channel 0 SSRx_i0 109 H 04DA DTCEG2 SSTx_i0 110 H 04DC DTCEG1 Low Note DTCE bits with no corresponding interrupt are reserved and the write value should aslways be 0 8 5 Operation Register information is stored in on chip RAM When activated the DTC reads register information in on chip RAM and t...

Page 144: ...er SAR and DAR are independently incremented decremented or left fixed depending on its register information Start End Read DTC vector Read register information Data transfer Write register information Clear an activation flag Interrupt exception handling Clear DTCER CHNE 1 Next transfer Yes Yes No Transfer Counter 0 or DISEL 1 No Figure 8 4 Flowchart of DTC Operation ...

Page 145: ...d number of transfers have been completed a CPU interrupt can be requested Table 8 2 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used SAR DAR Transfer Figure...

Page 146: ...is repeated In repeat mode the transfer counter value does not reach H 00 and therefore CPU interrupts cannot be requested when DISEL 0 Table 8 3 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of transfers DTC...

Page 147: ... register is then incremented decremented or left fixed From 1 to 65 536 transfers can be specified Once the specified number of transfers have been completed a CPU interrupt is requested Table 8 4 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC t...

Page 148: ...ormation at that start address After data transfer ends the CHNE bit will be tested When it has been set to 1 DTC reads the next register information located in a consecutive area and performs the data transfer These sequences are repeated until the CHNE bit is cleared to 0 In the case of transfer with CHNE set to 1 an interrupt request to the CPU is not generated at the end of the specified numbe...

Page 149: ...pt SWDTEND is generated When the DISEL bit is 1 and one data transfer has been completed or the specified number of transfers have been completed after data transfer ends the SWDTE bit is held at 1 and an SWDTEND interrupt is generated The interrupt handling routine will then clear the SWDTE bit to 0 When the DTC is activated by software an SWDTEND interrupt is not generated during a data transfer...

Page 150: ...e of 2 φ DTC activation request DTC request Address Vector read Read Write Read Write Data transfer Data transfer Transfer information write Transfer information write Transfer information read Transfer information read Figure 8 11 DTC Operation Timing Example of Chain Transfer 8 5 7 Number of DTC Execution States Table 8 5 lists execution status for a single DTC data transfer and table 8 6 shows ...

Page 151: ... 1 Byte data read SK 1 1 2 2 2 3 m 2 3 m Word data read SK 1 1 4 2 4 6 2m 2 3 m Byte data write SL 1 1 2 2 2 3 m 2 3 m Word data write SL 1 1 4 2 4 6 2m 2 3 m Internal operation SM 1 Note Not available in this LSI The number of execution states is calculated from using the formula below Note that Σ is the sum of all transfers activated by one activation source the number in which the CHNE bit is s...

Page 152: ...et the start address of the register information in the DTC vector address 3 Check that the SWDTE bit is 0 4 Write 1 to SWDTE bit and the vector number to DTVECR 5 Check the vector number written to DTVECR 6 After one data transfer has been completed if the DISEL bit is 0 and a CPU interrupt is not requested the SWDTE bit is cleared to 0 If the DTC is to continue transferring data set the SWDTE bi...

Page 153: ...g of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer transfer when CHNE 0 1 Perform settings for transfer to the PPG s NDR Set MRA to incrementing source address SM1 1 SM0 0 a fixed destination address DM1 DM0 0 repeat mode MD1 0 MD0 1 and word size Sz 1 Set the source side as a repeat area DTS 1...

Page 154: ...000 in SAR the destination address H 2000 in DAR and 128 H 8080 in CRA Set 1 H 0001 in CRB 2 Set the start address of the register information at the DTC vector address H 04C0 3 Check that the SWDTE bit in DTVECR is 0 Check that there is currently no transfer activated by software 4 Write 1 to the SWDTE bit and the vector number H 60 to DTVECR The write data is H E0 5 Read DTVECR again and check t...

Page 155: ...C is used the RAME bit in SYSCR must not be cleared to 0 8 8 3 DTCE Bit Setting For DTCE bit setting use bit manipulation instructions such as BSET and BCLR If all interrupts are masked multiple activation sources can be set at one time only at the initial setting by writing data after executing a dummy read on the relevant register ...

Page 156: ...Rev 1 0 09 02 page 120 of 568 ...

Page 157: ...tput a data register DR that stores output data and a port register PORT used to read the pin states The input only ports do not have a DR or DDR register Ports A to D have built in input pull up MOS functions and input pull up MOS control registers PCR to control the on off state of input pull up MOS Ports A to C include an open drain control register ODR that controls the on off state of the out...

Page 158: ...IOCA1 IRQ0 P13 PO11 TIOCD0 TCLKB P12 PO10 TIOCC0 TCLKA P11 PO9 TIOCB0 P10 PO8 TIOCA0 Port 3 General I O port also functioning as SCI_0 I O pins and interrupt input pins P37 P36 P35 IRQ5 P34 P33 P32 SCK0 IRQ4 P31 RxD0 P30 TxD0 Port 4 General input port also functioning as A D converter analog inputs P47 AN7 P46 AN6 P45 AN5 P44 AN4 P43 AN3 P42 AN2 P41 AN1 P40 AN0 Port 7 General I O port also functio...

Page 159: ...2 PA1 TxD2 PA0 Built in input pull up MOS Push pull or open drain output selectable Port B General I O port also functioning as TPU_5 TPU_4 and TPU_3 I O pins PB7 TIOCB5 PB6 TIOCA5 PB5 TIOCB4 PB4 TIOCA4 PB3 TIOCD3 PB2 TIOCC3 PB1 TIOCB3 PB0 TIOCA3 Built in input pull up MOS Push pull or open drain output selectable Port C General I O port also functioning as SSU_0 and SSU_1 I O pins PC7 SCS1 PC6 SS...

Page 160: ...ut and Output Type Port D General I O port PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Built in input pull up MOS Port F General I O port also functioning as interrupt input pins an A D converter start trigger input pin and a system clock output pin φ PF7 φ PF6 PF5 PF4 PF3 ADTRG IRQ3 PF2 PF1 PF0 IRQ2 ...

Page 161: ...ster the individual bits of which specify input or output for the pins of port 1 P1DDR cannot be read if it is an undefined value will be read Bit Bit Name Initial Value R W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W When a pin is specified as a general purpose I O port setting this bit to 1 makes the corresponding port 1 pin...

Page 162: ...ed as a general purpose I O port 9 1 3 Port 1 Register PORT1 PORT1 is an 8 bit read only register that shows the pin states PORT1 cannot be modified Bit Bit Name Initial Value R W Description 7 P17 Undefined R 6 P16 Undefined R 5 P15 Undefined R 4 P14 Undefined R 3 P13 Undefined R 2 P12 Undefined R 1 P11 Undefined R 0 P10 Undefined R If a port 1 read is performed while P1DDR bits are set to 1 the ...

Page 163: ... channel specification refer to section 10 16 Bit Timer Pulse Unit TPU Table 9 3 P16 Pin Function TPU Channel 2 Setting Output Input or Initial Value P16DDR 0 1 1 NDER14 0 1 Pin function TIOCA2 output P16 input P16 output PO14 output TIOCA2 input IRQ1 input Note For details on the TPU channel specification refer to section 10 16 Bit Timer Pulse Unit TPU Table 9 4 P15 Pin Function TPU Channel 1 Set...

Page 164: ...TPU Channel 0 Setting Output Input or Initial Value P13DDR 0 1 1 NDER11 0 1 Pin function TIOCD0 output P13 input P13 output PO11 output TIOCD0 input TCLKB input Note For details on the TPU channel specification refer to section 10 16 Bit Timer Pulse Unit TPU Table 9 7 P12 Pin Function TPU Channel 0 Setting Output Input or Initial Value P12DDR 0 1 1 NDER10 0 1 Pin function TIOCC0 output P12 input P...

Page 165: ... or Initial Value P10DDR 0 1 1 NDER8 0 1 Pin function TIOCA0 output P10 input P10 output PO8 output TIOCA0 input Note For details on the TPU channel specification refer to section 10 16 Bit Timer Pulse Unit TPU 9 2 Port 3 Port 3 is an 8 bit I O port and has the following registers Port 3 data direction register P3DDR Port 3 data register P3DR Port 3 register PORT3 Port 3 open drain control registe...

Page 166: ...t pin Clearing this bit to 0 makes the pin an input pin 9 2 2 Port 3 Data Register P3DR P3DR is an 8 bit readable writable register that stores output data for port 3 pins Bit Bit Name Initial Value R W Description 7 P37DR 0 R W 6 P36DR 0 R W 5 P35DR 0 R W 4 P34DR 0 R W 3 P33DR 0 R W 2 P32DR 0 R W 1 P31DR 0 R W 0 P30DR 0 R W Output data for a pin is stored when the pin is specified as a general I ...

Page 167: ...gister that specifies the output type of port 3 Bit Bit Name Initial Value R W Description 7 P37ODR 0 R W 6 P36ODR 0 R W 5 P35ODR 0 R W 4 P34ODR 0 R W 3 P33ODR 0 R W 2 P32ODR 0 R W 1 P31ODR 0 R W 0 P30ODR 0 R W When a pin is specified as an output port setting the corresponding bit to 1 specifies pin output to open drain and the input pull up MOS to the off state Clearing this bit to 0 specifies t...

Page 168: ...Pin Function P34DDR 0 1 Pin function P34 input P34 output Table 9 14 P33 Pin Function P33DDR 0 1 Pin function P33 input P33 output Table 9 15 P32 Pin Function CKE1 in SCR_0 0 1 C A in SMR_0 0 1 CKE0 in SCR_0 0 1 P32DDR 0 1 Pin function P32 input P32 output SCK0 output SCK0 output SCK0 input IRQ4 input Table 9 16 P31 Pin Function RE in SCR_0 0 1 P31DDR 0 1 Pin function P31 input P31 output RxD0 out...

Page 169: ...t 4 register PORT4 9 3 1 Port 4 Register PORT4 PORT4 is an 8 bit read only register that shows port 4 pin states Bit Bit Name Initial Value R W Description 7 P47 Undefined R 6 P46 Undefined R 5 P45 Undefined R 4 P44 Undefined R 3 P43 Undefined R 2 P42 Undefined R 1 P41 Undefined R 0 P40 Undefined R The pin states are always read when a port 4 read is performed Note Determined by the states of pins...

Page 170: ... a general purpose I O port setting this bit to 1 makes the corresponding port 7 pin an output pin Clearing this bit to 0 makes the pin an input pin 9 4 2 Port 7 Data Register P7DR P7DR is an 8 bit readable writable register that stores output data for port 7 pins Bit Bit Name Initial Value R W Description 7 P77DR 0 R W 6 P76DR 0 R W 5 P75DR 0 R W 4 P74DR 0 R W 3 P73DR 0 R W 2 P72DR 0 R W 1 P71DR ...

Page 171: ...ed by the states of pins P77 to P70 9 4 4 Pin Functions Port 7 pins also function as TMR_3 TMR_2 TMR_1 and TMR_0 I O pins The correspondence between the register specification and the pin functions is shown below Table 9 18 P77 Pin Function P77DDR 0 1 Pin function P77 input P77 output Table 9 19 P76 Pin Function P76DDR 0 1 Pin function P76 input P76 output Table 9 20 P75 Pin Function OSC3 to OSC0 ...

Page 172: ...t Table 9 24 P71 Pin Function P71DDR 0 1 Pin function P71 input P71 output TMCI23 input TMRI23 input Table 9 25 P70 Pin Function P70DDR 0 1 Pin function P70 input P70 output TMCI01 input TMRI01 input 9 5 Port 9 Port 9 is an input only port Port 9 pins also function as A D converter analog input pins Port 9 has the following register Port 9 register PORT9 9 5 1 Port 9 Register PORT9 PORT9 is an 8 b...

Page 173: ...scription 7 P97 Undefined R 6 P96 Undefined R 5 P95 Undefined R 4 P94 Undefined R 3 P93 Undefined R 2 P92 Undefined R 1 P91 Undefined R 0 P90 Undefined R The pin states are always read when a port 9 read is performed Note Determined by the states of pins P97 to P90 ...

Page 174: ...ata Direction Register PADDR PADDR is an 8 bit write only register the individual bits of which specify whether the pins of port A are used for input or output Bit Bit Name Initial Value R W Description 7 to 4 Undefined Reserved These bits are read as undefined value and cannot be modified 3 PA3DDR 0 W 2 PA2DDR 0 W 1 PA1DDR 0 W 0 PA0DDR 0 W When a pin is specified as a general purpose I O port set...

Page 175: ...ata for a pin is stored when the pin is specified as a general purpose I O port 9 6 3 Port A Register PORTA PORTA is an 8 bit read only register that shows port A pin states Bit Bit Name Initial Value R W Description 7 to 4 Undefined Reserved These bits are read as an undefined value 3 PA3 0 R 2 PA2 0 R 1 PA1 0 R 0 PA0 0 R If a port A read is performed while PADDR bits are set to 1 the PADR values...

Page 176: ...esponding bit to 1 turns on the input pull up MOS for that pin 9 6 5 Port A Open Drain Control Register PAODR PAODR is an 8 bit readable writable register that specifies the output type of port A Bit Bit Name Initial Value R W Description 7 to 4 Undefined Reserved These bits are read as an undefined value and cannot be modified 3 PA3ODR 0 R W 2 PA2ODR 0 R W 1 PA1ODR 0 R W 0 PA0ODR 0 R W When a pin...

Page 177: ...ion CKE1 in SCR_2 0 1 C A in SMR_2 0 1 CKE0 in SCR_2 0 1 PA3DDR 0 1 Pin function PA3 input PA3 output SCK2 output SCK2 output SCK2 input Table 9 27 PA2 Pin Function RE in SCR_2 0 1 PA2DDR 0 1 Pin function PA2 input PA2 output RxD2 input Table 9 28 PA1 Pin Function TE in SCR_2 0 1 PA1DDR 0 1 Pin function PA1 input PA1 output TxD2 output Table 9 29 PA0 Pin Function PA0DDR 0 1 Pin function PA0 input ...

Page 178: ...ODR 9 7 1 Port B Data Direction Register PBDDR PBDDR is an 8 bit write only register the individual bits of which specify whether the pins of port B are used for input or output Bit Bit Name Initial Value R W Description 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR 0 W When a pin is specified as a general purpose I O port setting this bit to 1...

Page 179: ...a for a pin is stored when the pin is specified as a general purpose I O port 9 7 3 Port B Register PORTB PORTB is an 8 bit read only register that shows port B pin states Bit Bit Name Initial Value R W Description 7 PB7 0 R 6 PB6 0 R 5 PB5 0 R 4 PB4 0 R 3 PB3 0 R 2 PB2 0 R 1 PB1 0 R 0 PB0 0 R If a port B read is performed while PBDDR bits are set to 1 the PBDR values are read If a port B read is ...

Page 180: ... setting the corresponding bit to 1 turns on the input pull up MOS for that pin 9 7 5 Port B Open Drain Control Register PBODR PBODR is an 8 bit readable writable register that specifies the output type of port B Bit Bit Name Initial Value R W Description 7 PB7ODR 0 R W 6 PB6ODR 0 R W 5 PB5ODR 0 R W 4 PB4ODR 0 R W 3 PB3ODR 0 R W 2 PB2ODR 0 R W 1 PB1ODR 0 R W 0 PB0ODR 0 R W When a pin function is s...

Page 181: ...Input or Initial Value PB6DDR 0 1 Pin function TIOCA5 output PB6 input PB6 output TIOCA5 input Note For details on the TPU channel specification refer to section 10 16 Bit Timer Pulse Unit TPU Table 9 32 PB5 Pin Function TPU channel 4 setting Output Input or Initial Value PB5DDR 0 1 Pin function TIOCB4 output PB5 input PB5 output TIOCB4 input Note For details on the TPU channel specification refer...

Page 182: ...fer to section 10 16 Bit Timer Pulse Unit TPU Table 9 36 PB1 Pin Function TPU channel 3 setting Output Input or Initial Value PB1DDR 0 1 Pin function TIOCB3 output PB1 input PB1 output TIOCB3 input Note For details on the TPU channel specification refer to section 10 16 Bit Timer Pulse Unit TPU Table 9 37 PB0 Pin Function TPU channel 3 setting Output Input or Initial Value PB0DDR 0 1 Pin function ...

Page 183: ...DDR 0 W 4 PC4DDR 0 W 3 PC3DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W 0 PC0DDR 0 W When a pin is specified as a general purpose I O port setting this bit to 1 makes the corresponding port 1 pin an output pin Clearing this bit to 0 makes the pin an input pin 9 8 2 Port C Data Register PCDR PCDR is an 8 bit readable writable register that stores output data for the port C pins Bit Bit Name Initial Value R W D...

Page 184: ...d Note Determined by the states of pins PC7 to PC0 9 8 4 Port C Pull Up MOS Control Register PCPCR PCPCR is an 8 bit readable writable register that controls the on off state of input pull up MOS of port C Bit Bit Name Initial Value R W Description 7 PC7PCR 0 R W 6 PC6PCR 0 R W 5 PC5PCR 0 R W 4 PC4PCR 0 R W 3 PC3PCR 0 R W 2 PC2PCR 0 R W 1 PC1PCR 0 R W 0 PC0PCR 0 R W When a pin is specified as an i...

Page 185: ...MOS to the off state Clearing this bit to 0 specifies push pull output 9 8 6 Pin Functions Port C pins also function as SSU_1 and SSU_0 I O pins The correspondence between the register specification and the pin functions is shown below Table 9 38 PC7 Pin Function CSS1 0 1 CSS0 0 1 0 1 PC7DDR 0 1 Pin function PC7 input PC7 output SCS1 input SCS1 input output auto switch Setting prohibited Table 9 3...

Page 186: ...0 1 1 PC4DDR 0 1 0 1 0 1 SCSI input 0 1 Pin function PC4 in put PC4 out put SSO1 in put PC4 in put PC4 out put SSO1 out put PC4 in put PC4 out put SSO1 in put Set ting pro hibited SSO1 out put SSO1 Hi z SSO1 out put Table 9 42 PC3 Pin Function CSS1 0 1 CSS0 0 1 0 1 PC3DDR 0 1 Pin function PC3 input PC3 output SCS0 input SCS0 input output auto switch Setting prohibited Table 9 43 PC2 Pin Function M...

Page 187: ... output PC1 input PC1 output PC1 input PC1 output SSI0 input PC1 input PC1 output Table 9 45 PC 0Pin Function MSS 0 1 0 1 BIDE 0 1 RE 0 1 0 1 0 TE 0 1 0 0 1 1 PC0DDR 0 1 0 1 0 1 0 1 Pin function PC0 in put PC0 out put SSO0 in put PC0 in put PC0 out put SSO0 out put PC0 in put PC0 out put SSO0 input Setting pro hibited SSO0 out put SSO0 Hi z SSO0 out put ...

Page 188: ...DR Port D register PORTD Port D pull up MOS control register PDPCR Port D realtime input data register PDRTIDR 9 9 1 Port D Data Direction Register PDDDR PDDDR is an 8 bit write only register the individual bits of which specify whether the pins of port D are used for input or output Bit Bit Name Initial Value R W Description 7 PD7DDR 0 W 6 PD6DDR 0 W 5 PD5DDR 0 W 4 PD4DDR 0 W 3 PD3DDR 0 W 2 PD2DD...

Page 189: ...D is an 8 bit read only register that shows port D pin states Bit Bit Name Initial Value R W Description 7 PD7 Undefined R 6 PD6 Undefined R 5 PD5 Undefined R 4 PD4 Undefined R 3 PD3 Undefined R 2 PD2 Undefined R 1 PD1 Undefined R 0 PD0 Undefined R If a port D read is performed while PDDDR bits are set to 1 the PDDR values are read If a port D read is performed while PDDDR bits are cleared to 0 th...

Page 190: ...put The falling rising or both edges of the IRQ3 pin can be specified as a trigger timing by bits 7 and 6 in the IRQ sense control register L ISCRL For details of this setting see section 5 3 3 IRQ Sense Control Registers H and L ISCRH ISCRL Bit Bit Name Initial Value R W Description 7 PDRTIDR7 0 R W 6 PDRTIDR6 0 R W 5 PDRTIDR5 0 R W 4 PDRTIDR4 0 R W 3 PDRTIDR3 0 R W 2 PDRTIDR2 0 R W 1 PDRTIDR1 0 ...

Page 191: ...ption 7 PF7DDR 0 W When a pin is specified as a general purpose I O port setting this bit to 1 makes the PF7 pin a φ output pin Clearing this bit to 0 makes the pin an input pin 6 PF6DDR 0 W 5 PF5DDR 0 W 4 PF4DDR 0 W 3 PF3DDR 0 W 2 PF2DDR 0 W 1 PF1DDR 0 W 0 PF0DDR 0 W When a pin is specified as a general purpose I O port setting this bit to 1 makes the corresponding port F pin an output pin Cleari...

Page 192: ...n the pin is specified as a general purpose I O port 9 10 3 Port F Register PORTF PORTF is an 8 bit read only register that shows port F pin states PORTF cannot be modified Bit Bit Name Initial Value R W Description 7 PF7 Undefined R 6 PF6 Undefined R 5 PF5 Undefined R 4 PF4 Undefined R 3 PF3 Undefined R 2 PF2 Undefined R 1 PF1 Undefined R 0 PF0 Undefined R If a port F read is performed while PFDD...

Page 193: ...F6 output Table 9 48 PF5 Pin Function PF5DDR 0 1 Pin function PF5 input PF5 output Table 9 49 PF4 Pin Function PF4DDR 0 1 Pin function PF4 input PF4 output Table 9 50 PF3 Pin Function PF3DDR 0 1 Pin function PF3 input PF3 output ADTRG input 1 IRQ3 input 2 Notes 1 ADTRG input when TRGS0 TRGS1 1 2 When used as an external interrupt input pin do not use as an I O pin for another function This pin als...

Page 194: ... PF1 Pin Function PF1DDR 0 1 Pin function PF1 input PF1 output Table 9 53 PF0 Pin Function PF0DDR 0 1 Pin function PF0 input PF0 output IRQ2 input Note When used as an external interrupt input pin do not use as an I O pin for another function ...

Page 195: ...onous operation Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input output is possible by synchronous counter operation A maximum 15 phase PWM output is possible in combination with synchronous operation Buffer operation settable for channels 0 and 3 Phase counting mode settable independently...

Page 196: ...GRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRA_4 TGRB_4 TGRA_5 TGRB_5 General registers buffer registers TGRC_0 TGRD_0 TGRC_3 TGRD_3 I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input...

Page 197: ...ch or input capture TGRA_2 TGRB_2 compare match or input capture TGRA_3 TGRB_3 compare match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 sources Compare ma...

Page 198: ...ntrol register Timer mode register Timer I O control registers H L Timer interrupt enable register Timer status register TImer general registers A B C D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3 Channel 4 Channel 5 Interrupt request signals Channel 3 Channel 4 Channel 5 Internal data bus PPG output trigger signal A D converter conversion start sign...

Page 199: ...mpare output PWM output pin 1 TIOCA1 I O TGRA_1 input capture input output compare output PWM output pin TIOCB1 I O TGRB_1 input capture input output compare output PWM output pin 2 TIOCA2 I O TGRA_2 input capture input output compare output PWM output pin TIOCB2 I O TGRB_2 input capture input output compare output PWM output pin 3 TIOCA3 I O TGRA_3 input capture input output compare output PWM ou...

Page 200: ...r general register C_0 TGRC_0 Timer general register D_0 TGRD_0 Timer control register_1 TCR_1 Timer mode register_1 TMDR_1 Timer I O control register _1 TIOR_1 Timer interrupt enable register_1 TIER_1 Timer status register_1 TSR_1 Timer counter_1 TCNT_1 Timer general register A_1 TGRA_1 Timer general register B_1 TGRB_1 Timer control register_2 TCR_2 Timer mode register_2 TMDR_2 Timer I O control...

Page 201: ...ter _4 TIOR_4 Timer interrupt enable register_4 TIER_4 Timer status register_4 TSR_4 Timer counter_4 TCNT_4 Timer general register A_4 TGRA_4 Timer general register B_4 TGRB_4 Timer control register_5 TCR_5 Timer mode register_5 TMDR_5 Timer I O control register_5 TIOR_5 Timer interrupt enable register_5 TIER_5 Timer status register_5 TSR_5 Timer counter_5 TCNT_5 Timer general register A_5 TGRA_5 ...

Page 202: ... These bits select the input clock edge When the input clock is counted using both edges the input clock period is halved e g φ 4 both edges φ 2 rising edge If phase counting mode is used on channels 1 2 4 and 5 this setting is ignored and the phase counting mode setting has priority Internal clock edge selection is valid when the input clock is φ 4 or slower This setting is ignored if the input c...

Page 203: ...aring synchronous operation 1 Notes 1 Synchronous operation is set by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is not cleared because the buffer register setting has priority and compare match input capture does not occur Table 10 4 CCLR0 to CCLR2 Channels 1 2 4 and 5 Channel Bit 7 Reserved 2 Bit 6 CCLR1 Bit 5 CCLR0 Description 1 2 4 5 0 0 0 TCNT clea...

Page 204: ... 1 0 External clock counts on TCLKC pin input 1 External clock counts on TCLKD pin input Table 10 6 TPSC0 to TPSC2 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 1 0 0 0 Internal clock counts on φ 1 1 Internal clock counts on φ 4 1 0 Internal clock counts on φ 16 1 Internal clock counts on φ 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKB pin i...

Page 205: ...B pin input 1 0 External clock counts on TCLKC pin input 1 Internal clock counts on φ 1024 Note This setting is ignored when channel 2 is in phase counting mode Table 10 8 TPSC0 to TPSC2 Channel 3 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock counts on φ 1 1 Internal clock counts on φ 4 1 0 Internal clock counts on φ 16 1 Internal clock counts on φ 64 1 0 0 Externa...

Page 206: ... 1024 1 Counts on TCNT5 overflow underflow Note This setting is ignored when channel 4 is in phase counting mode Table 10 10 TPSC0 to TPSC2 Channel 5 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 0 Internal clock counts on φ 1 1 Internal clock counts on φ 4 1 0 Internal clock counts on φ 16 1 Internal clock counts on φ 64 1 0 0 External clock counts on TCLKA pin input 1 External cl...

Page 207: ...ompare is not generated In channels 1 2 4 and 5 which have no TGRD bit 5 is reserved It is always read as 0 and cannot be modified 0 TGRB operates normally 1 TGRB and TGRD used together for buffer operation 4 BFA 0 R W Buffer Operation A Specifies whether TGRA is to operate in the normal way or TGRA and TGRC are to be used together for buffer operation When TGRC is used as a buffer register TGRC i...

Page 208: ...rved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 X X X Legend X Don t care Notes 1 MD3 is a reserved bit In a write it should always be written with 0 2 Phase counting mode cannot be set for channels 0 and 3 In this case 0 should always be written to MD2 ...

Page 209: ...cleared to 0 is specified When TGRC or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register TIORH_0 TIOR_1 TIOR_2 TIORH_3 TIOR_4 TIOR_5 Bit Bit Name Initial value R W Description 7 6 5 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 R W R W R W R W I O Control B0 to B3 Specify the function of TGRB 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R W R W R W R W I O Contr...

Page 210: ... 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCB0 pin Input capture at rising edge 1 Capture input source is the TIOCB0 pin Input capture at falling edge 1 X Capture input source is the TIOCB0 pin Input capture at both edges 1 X X Input capture register Capture input source is channel 1 count clock I...

Page 211: ...e output at compare match 1 0 0 0 Capture input source is the TIOCD0 pin Input capture at rising edge 1 Capture input source is the TIOCD0 pin Input capture at falling edge 1 X Capture input source is the TIOCD0 pin Input capture at both edges 1 X X Input capture register 2 Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down 1 Legend X Don t care Notes 1 When ...

Page 212: ...led 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCB1 pin Input capture at rising edge 1 Capture input source is the TIOCB1 pin Input capture at falling edge 1 X Capture input source is the TIOCB1 pin Input capture at both edges 1 X...

Page 213: ...s 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 X 0 0 Capture input source is the TIOCB2 pin Input capture at rising edge 1 Capture input source is the TIOCB2 pin Input capture at falling edge 1 X Input capture reg...

Page 214: ... 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCB3 pin Input capture at rising edge 1 Capture input source is the TIOCB3 pin Input capture at falling edge 1 X Capture input source is the TIOCB3 pin Input capture at both edges 1 X X Input capture register Capture input source is channel 4 count clock I...

Page 215: ...e output at compare match 1 0 0 0 Capture input source is the TIOCD3 pin Input capture at rising edge 1 Capture input source is the TIOCD3 pin Input capture at falling edge 1 X Capture input source is the TIOCD3 pin Input capture at both edges 1 X X Input capture register 2 Capture input source is channel 4 count clock Input capture at TCNT_4 count up count down 1 Legend X Don t care Notes 1 When ...

Page 216: ...l output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCB4 pin Input capture at rising edge 1 Capture input source is the TIOCB4 pin Input capture at falling edge 1 X Capture input source is the TIOCB4 pin Input capture at both edges 1 X X Input cap...

Page 217: ...s 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 X 0 0 Capture input source is the TIOCB5 pin Input capture at rising edge 1 Capture input source is the TIOCB5 pin Input capture at falling edge 1 X Input capture reg...

Page 218: ... disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCA0 pin Input capture at rising edge 1 Capture input source is the TIOCA0 pin Input capture at falling edge 1 X Capture input source is the TIOCA0 pin Input capture at both edg...

Page 219: ... 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCC0 pin Input capture at rising edge 1 Capture input source is the TIOCC0 pin Input capture at falling edge 1 X Capture input source is the TIOCC0 pin Input capture at both edges 1 X X Input capture register Capture input source is channel 1 count clock I...

Page 220: ...put is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCA1 pin Input capture at rising edge 1 Capture input source is the TIOCA1 pin Input capture at falling edge 1 X Capture input source is the TIOCA1 pin Input capture at both edges 1 X X Input capture ...

Page 221: ...s 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 X 0 0 Capture input source is the TIOCA2 pin Input capture at rising edge 1 Capture input source is the TIOCA2 pin Input capture at falling edge 1 X Input capture reg...

Page 222: ... disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCA3 pin Input capture at rising edge 1 Capture input source is the TIOCA3 pin Input capture at falling edge 1 X Capture input source is the TIOCA3 pin Input capture at both edg...

Page 223: ... 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCC3 pin Input capture at rising edge 1 Capture input source is the TIOCC3 pin Input capture at falling edge 1 X Capture input source is the TIOCC3 pin Input capture at both edges 1 X X Input capture register Capture input source is channel 4 count clock I...

Page 224: ...l output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 0 0 0 Capture input source is the TIOCA4 pin Input capture at rising edge 1 Capture input source is the TIOCA4 pin Input capture at falling edge 1 X Capture input source is the TIOCA4 pin Input capture at both edges 1 X X Input cap...

Page 225: ...s 0 Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 Initial output is 1 1 output at compare match 1 Output compare register Initial output is 1 Toggle output at compare match 1 X 0 0 Capture input source is the TIOCA5 pin Input capture at rising edge 1 Capture input source is the TIOCA5 pin Input capture at falling edge 1 X Input capture reg...

Page 226: ...ble Enables or disables interrupt requests TCIU by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 2 4 and 5 In channels 0 and 3 bit 5 is reserved It is always read as 0 and cannot be modified 0 Interrupt requests TCIU by TCFU disabled 1 Interrupt requests TCIU by TCFU enabled 4 TCIEV 0 R W Overflow Interrupt Enable Enables or disables interrupt requests TCIV by the TCFV flag whe...

Page 227: ...uests TGIC by TGFC bit disabled 1 Interrupt requests TGIC by TGFC bit enabled 1 TGIEB 0 R W TGR Interrupt Enable B Enables or disables interrupt requests TGIB by the TGFB bit when the TGFB bit in TSR is set to 1 0 Interrupt requests TGIB by TGFB bit disabled 1 Interrupt requests TGIB by TGFB bit enabled 0 TGIEA 0 R W TGR Interrupt Enable A Enables or disables interrupt requests TGIA by the TGFA bi...

Page 228: ...ys read as 1 and cannot be modified 5 TCFU 0 R W Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 2 4 and 5 are set to phase counting mode Only 0 can be written for flag clearing In channels 0 and 3 bit 5 is reserved It is always read as 0 and cannot be modified Setting condition When the TCNT value underflows changes from H 0000 to H FFFF Clearing conditi...

Page 229: ...ng conditions When DTC is activated by TGID interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD 1 2 TGFC 0 R W Input Capture Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3 Only 0 can be written for flag clearing In channels 1 2 4 and 5 bit 2 is reserved It is always read as 0 and can...

Page 230: ...ng conditions When DTC is activated by TGIB interrupt and the DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 0 TGFA 0 R W Input Capture Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match Only 0 can be written for flag clearing Setting conditions When TCNT TGRA and TGRA is functioning as output compare register When TC...

Page 231: ...st always be accessed as a 16 bit unit TGR buffer register combinations are TGRA TGRC and TGRB TGRD 10 3 8 Timer Start Register TSTR TSTR is an 8 bit readable writable register that selects operation stoppage for channels 0 to 5 When setting the operating mode in TMDR or setting the count clock in TCR first stop the TCNT counter Bit Bit Name Initial value R W Description 7 6 All 0 Reserved The wri...

Page 232: ...ted the TCNT synchronous presetting of multiple channels and synchronous clearing by counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the SYNC bit the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR 0 TCNT_0 to TCNT_5 operates independently T...

Page 233: ...ompare register Set period Free running counter Start count operation Free running counter Periodic counter Start count operation Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodic counter operation select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR Designate the TGR ...

Page 234: ...ST bit TCFV Time Figure 10 3 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR After the settings have been mad...

Page 235: ...10 5 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode Set output timing Start count operation Waveform output Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value is output at the TIOC pin unit the first compare match occurs Set th...

Page 236: ...value H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 10 6 Example of 0 Output 1 Output Operation Figure 10 7 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing on compare match B and settings have been made such that the output is toggled by both compare match A and compar...

Page 237: ...ls 0 and 3 φ 1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if φ 1 is selected 1 Example of input capture operation setting procedure Figure 10 8 shows an example of the input capture operation setting procedure Input selection Select input capture input Start count Input capture operation Designate TGR as an input capture regis...

Page 238: ...ted as the TIOCA pin input capture input edge the falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT value H 0180 H 0000 TIOCA TGRA H 0010 H 0005 Counter cleared by TIOCB input falling edge H 0160 H 0005 H 0160 H 0010 TGRB H 0180 TIOCB Time Figure 10 9 Example of Input Capture Operation ...

Page 239: ...ous presetting Set TCNT Synchronous presetting Counter clearing Synchronous clearing Synchronous clearing Clearing source generation channel Select counter clearing source Start count Set synchronous counter clearing Start count Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation When the TCNT counter of any of the channels designated for synchro...

Page 240: ...clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters and the data set in TGRB_0 is used as the PWM cycle For details of PWM modes see section 10 4 5 PWM Modes TCNT0 to TCNT2 values H 0000 TIOCA_0 TIOCA_1 TGRB_0 Synchronous clearing by TGRB_0 compare match TGRA_2 TGRA_1 TGRB_2 TGRA_0 TGRB_1 TIOCA_2 Time Figure 10 11 Example of Synchronous Operation 10 4 3 Buffer Operation...

Page 241: ...ure 10 12 Buffer register Timer general register TCNT Comparator Compare match signal Figure 10 12 Compare Match Buffer Operation When TGR is an input capture register When input capture occurs the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register This operation is illustrated in figure 10 13 Buffer register Timer ...

Page 242: ...in which PWM mode 1 has been designated for channel 0 and buffer operation has been designated for TGRA and TGRC The settings used in this example are TCNT clearing by compare match B 1 output at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer...

Page 243: ...RA input capture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value is stored in TGRA upon the occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC TCNT value H 09FB H 0000 TGRC Time H 0532 TIOCA TGRA H 0F07 H 0532 H 0F07 H 0532 H...

Page 244: ...NT_2 Channels 4 and 5 TCNT_4 TCNT_5 Example of Cascaded Operation Setting Procedure Figure 10 17 shows an example of the setting procedure for cascaded operation Cascaded operation Set cascading Start count Cascaded operation Set bits TPSC2 to TPSC0 in the channel 1 channel 4 TCR to B 1111 to select TCNT_2 TCNT_5 overflow underflow counting Set the CST bit in TSTR for the upper and lower channel t...

Page 245: ..._2 underflow TCLKA TCNT_2 FFFD TCNT_1 0001 TCLKB FFFE FFFF 0000 0001 0002 0001 0000 FFFF 0000 0000 Figure 10 19 Example of Cascaded Operation 2 10 4 5 PWM Modes In PWM mode PWM waveforms are output from the output pins The output level can be selected as 0 1 or toggle output in response to a compare match of each TGR TGR registers settings can be used to output a PWM waveform in the range of 0 to ...

Page 246: ...GR as the cycle register and the others as duty cycle registers The output specified in TIOR is performed by means of compare matches Upon counter clearing by a synchronization register compare match the output value of each pin is the initial value set in TIOR If the set values of the cycle and duty cycle registers are identical the output value does not change when a compare match occurs In PWM ...

Page 247: ...EG1 and CKEG0 in TCR Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source Use TIOR to designate the TGR as an output compare register and select the initial value and output value Set the cycle in the TGR selected in 2 and set the duty in the other the TGR Select the PWM mode with bits MD3 to MD0 in TMDR Set the CST bit in TSTR to 1 start the count operation 1 2 ...

Page 248: ...r the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 outputting a 5 phase PWM waveform In this case the value set in TGRB_1 is used as the cycle and the values set in the other TGRs are used as the duty cycle levels TCNT value TGRB_1 H 0000 TIOCA0 Counter cleared by TGRB_1 compare match Time TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 TIOCB0 TIOCC0 TIOCD0...

Page 249: ...written TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously 0 duty Figure 10 23 Example of PWM Mode Operation 3 ...

Page 250: ...ng up the TCFV flag in TSR is set if underflow occurs when TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag reveals whether TCNT is counting up or down Table 10 31 shows the correspondence between external clock pins and channels Table 10 31 Phase Counting Mode Clock Input Pins External Clock Pins Channels A Phase B Phase When channel...

Page 251: ...unt Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 10 25 Example of Phase Counting Mode 1 Operation Table 10 32 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up count Low level Low level High level High level Down count Lo...

Page 252: ...ounting Mode 2 Operation Table 10 33 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care High level Don t care Low level Down count Legend Rising edge Falling edge ...

Page 253: ...LKB channels 1 and 5 TCLKD channels 2 and 4 Figure 10 27 Example of Phase Counting Mode 3 Operation Table 10 34 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care High leve...

Page 254: ...KC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 10 28 Example of Phase Counting Mode 4 Operation Table 10 35 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level Don t car...

Page 255: ...TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period TGRB_0 is used for input capture with TGRB_0 and TGRD_0 operating in buffer mode The channel 1 counter input clock is designated as the TGRB_0 input capture source and the pulse widths of 2 phase encoder 4 multiplication pulses are detected TGRA_1 and TGRB_1 for channel 1...

Page 256: ..._1 speed period capture TGRA_0 speed control period TGRB_1 speed period capture TGRC_0 position control period TGRB_0 pulse width capture TGRD_0 buffer operation Channel 0 TCLKA TCLKB Edge detection circuit Figure 10 29 Phase Counting Mode Application Example ...

Page 257: ...bled or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set to 1 at this time an interrupt is requested The interrupt request is cleared by clearing the status flag to 0 Relative channel priorities can be changed by the interrupt controller however the priority order within a channel is...

Page 258: ...e TCIV_2 TCNT_2 overflow TCFV_2 Not possible TCIU_2 TCNT_2 underflow TCFU_2 Not possible 3 TGIA_3 TGRA_3 input capture compare match TGFA_3 Possible TGIB_3 TGRB_3 input capture compare match TGFB_3 Possible TGIC_3 TGRC_3 input capture compare match TGFC_3 Possible TGID_3 TGRD_3 input capture compare match TGFD_3 Possible TCIV_3 TCNT_3 overflow TCFV_3 Not possible 4 TGIA_4 TGRA_4 input capture comp...

Page 259: ...ow on a channel The interrupt request is cleared by clearing the TCFU flag to 0 The TPU has four underflow interrupts one each for channels 1 2 4 and 5 10 6 DTC Activation The DTC can be activated by the TGR input capture compare match interrupt for a channel For details see section 8 Data Transfer Controller DTC A total of 16 TPU input capture compare match interrupts can be used as DTC activatio...

Page 260: ...clock External clock φ N 1 N N 1 N 2 Falling edge Rising edge Falling edge Figure 10 31 Count Timing in External Clock Operation Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match the point at which the count value matched by TCNT is updated When a compare match signal is generated the output value set in TIOR is output at the output com...

Page 261: ...33 shows input capture signal timing TCNT Input capture input N N 1 N 2 N N 2 TGR Input capture signal φ Figure 10 33 Input Capture Input Signal Timing Timing for Counter Clearing by Compare Match Input Capture Figure 10 34 shows the timing when counter clearing on compare match is specified and figure 10 35 shows the timing when counter clearing on input capture is specified ...

Page 262: ...568 TCNT Counter clear signal Compare match signal TGR N N H 0000 φ Figure 10 34 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal TGR N H 0000 N φ Figure 10 35 Counter Clear Timing Input Capture ...

Page 263: ...d 10 37 show the timing in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 φ Figure 10 36 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal TGRC TGRD N n n N 1 N N N 1 φ Figure 10 37 Buffer Operation Timing Input Capture ...

Page 264: ...signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt φ Figure 10 38 TGI Interrupt Timing Compare Match TGF Flag Setting Timing in Case of Input Capture Figure 10 39 shows the timing for setting of the TGF flag in TSR on input capture and TGI interrupt request signal timing TGR TCNT Input capture signal N N TGF flag TGI interrupt φ Figure 10 39 TGI Interrupt T...

Page 265: ... Figure 10 41 shows the timing for setting of the TCFU flag in TSR on underflow and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF H 0000 TCFV flag TCIV interrupt φ Figure 10 40 TCIV Interrupt Setting Timing Underflow signal TCNT underflow TCNT input clock H 0000 H FFFF TCFU flag TCIU interrupt φ Figure 10 41 TCIU Interrupt Setting Timing ...

Page 266: ...atus flag clearing by the CPU and figure 10 43 shows the timing for status flag clearing by the DTC Status flag Write signal Address TSR address Interrupt request signal TSR write cycle T1 T2 φ Figure 10 42 Timing for Status Flag Clearing by CPU Interrupt request signal Status flag Address Source address DTC read cycle T1 T2 Destination address T1 T2 DTC write cycle φ Figure 10 43 Timing for Statu...

Page 267: ...the phase difference and overlap between the two input clocks must be at least 1 5 states and the pulse width must be at least 2 5 states Figure 10 44 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width Pulse width Pulse width Notes Phase difference and overlap Pulse width 1 5 states or more 2 5...

Page 268: ...ons If the counter clear signal is generated in the T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 10 45 shows the timing in this case Counter clear signal Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 N H 0000 Figure 10 45 Conflict between TCNT Write and Clear Operations ...

Page 269: ...urs in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 10 46 shows the timing in this case TCNT input clock Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 10 46 Conflict between TCNT Write and Increment Operations ...

Page 270: ...rite takes precedence and the compare match signal is inhibited A compare match does not occur even if the previous value is written Figure 10 47 shows the timing in this case Compare match signal Write signal Address φ TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Inhibited Figure 10 47 Conflict between TGR Write and Compare Match ...

Page 271: ...he data that is transferred to TGR by the buffer operation will be that in the buffer prior to the write Figure 10 48 shows the timing in this case Compare match signal Write signal Address φ Buffer register address Buffer register TGR write cycle T1 T2 N TGR N M Buffer register write data Figure 10 48 Conflict between Buffer Register Write and Compare Match ...

Page 272: ...ed in the T1 state of a TGR read cycle the data that is read will be that in the buffer after input capture transfer Figure 10 49 shows the timing in this case Input capture signal Read signal Address φ TGR address TGR TGR read cycle T1 T2 M Internal data bus X M Figure 10 49 Conflict between TGR Read and Input Capture ...

Page 273: ...rated in the T2 state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 10 50 shows the timing in this case Input capture signal Write signal Address φ TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 10 50 Conflict between TGR Write and Input Capture ...

Page 274: ...r register write cycle the buffer operation takes precedence and the write to the buffer register is not performed Figure 10 51 shows the timing in this case Input capture signal Write signal Address φ TCNT Buffer register write cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 10 51 Conflict between Buffer Register Write and Input Capture ...

Page 275: ...ltaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 10 52 shows the operation timing when a TGR compare match is specified as the clearing source and when H FFFF is set in TGR Counter clear signal TCNT input clock φ TCNT TGF Disabled TCFV H FFFF H 0000 Figure 10 52 Conflict between Overflow and Counter Clearing ...

Page 276: ...g Figure 10 53 Conflict between TCNT Write and Overflow 10 9 13 Multiplexing of I O Pins In this LSI the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with the TIOCD0 I O pin the TCLKC input pin with the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin 10 9...

Page 277: ...ng the timer to be used for various applications such as the generation of pulse output or PWM output with an arbitrary duty cycle Cascading of the two channels Cascading of TMR_0 and TMR_1 The module can operate as a 16 bit timer using TMR_0 as the upper half and TMR_1 as the lower half 16 bit count mode TMR_1 can be used to count TMR_0 compare match occurrences compare match count mode Cascading...

Page 278: ..._1 TMCI01 TCNT_0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 A D conversion start request signal Clock select Control logic Clear 0 TCORA_1 TCORB_1 TCNT_1 TCSR_1 TCR_1 Time constant register A_1 Time constant register B_1 Timer counter_1 Timer control status register_1 Timer control register_1 Legend TCORA_0 TCORB_0 TCNT_0 TCSR_0 TCR_0 Time constant register A_0 Time constant regi...

Page 279: ...counter 11 3 Register Descriptions The 8 bit timer has the following registers For details on the module stop register refer to section 21 1 2 Module Stop Registers A to C MSTPCRA to MSTPCRC Timer counter_0 TCNT_0 Time constant register A_0 TCORA_0 Time constant register B_0 TCORB_0 Timer control register_0 TCR_0 Timer control status register_0 TCSR_0 Timer counter_1 TCNT_1 Time constant register ...

Page 280: ... compare match flag A CMFA in TCSR is set Note however that comparison is disabled during the T2 state of a TCORA write cycle The timer output from the TMO pin can be freely controlled by the compare match signal A and the settings of output select bits OS1 and OS0 in TCSR The initial value of TCORA is H FF 11 3 3 Time Constant Registers B TCORB TCORB is an 8 bit readable writable register TCORB_0...

Page 281: ... enabled or disabled when the CMFA flag in TCSR is set to 1 0 CMFA interrupt request CMIA is disabled 1 CMFA interrupt request CMIA is enabled 5 OVIE 0 R W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request OVI is enabled or disabled when the OVF flag in TCSR is set to 1 0 OVF interrupt request OVI is disabled 1 OVF interrupt request OVI is enabled 4 3 CCLR1 CCLR0 0 0 R W R ...

Page 282: ...source counted on the falling edge 011 φ 8192 internal clock source counted on the falling edge 100 For channel 0 Counted on TCNT1 overflow signal For channel 1 Counted on TCNT0 overflow signal For channel 2 Counted on TCNT3 overflow signal For channel 3 Counted on TCNT2 overflow signal 101 External clock source counted at rising edge 110 External clock source counted at falling edge 111 External ...

Page 283: ...RB of TDC 6 CMFA 0 R W Compare match Flag A Setting condition When TCNT TCORA Clearing condition Read CMFA when CMFA 1 then write 0 in CMFA DTC is activated by the CMIA interrupt and DISEL bit 0 in MRB of DTC 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNT overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 in OVF 4 ADTE 0 R W A D Trigger Enable Enables or d...

Page 284: ... 10 1 is output when compare match B occurs 11 Output is inverted when compare match B occurs toggle output 1 0 OS1 OS0 0 0 R W R W Output Select 1 and 0 These bits specify how the timer output level is to be changed by a compare match A of TCORA and TCNT 00 No change when compare match A occurs 01 0 is output when compare match A occurs 10 1 is output when compare match A occurs 11 Output is inve...

Page 285: ... DTC is activated by the CMIA interrupt and the DISEL bit 0 in MRB of DTC 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNT overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 in OVF 4 1 Reserved This bit is always read as 1 and cannot be modified 3 2 OS3 OS2 0 0 R W R W Output Select 3 and 2 These bits specify how the timer output level is to be changed by a ...

Page 286: ...tten to this bit to clear the flag TCSR_2 Bit Bit Name Initial Value R W Description 7 CMFB 0 R W Compare Match Flag B Setting condition When TCNT TCORB Clearing condition Read CMFB when CMFB 1 then write 0 in CMFB DTC is activated by the CMIB interrupt and the DISEL bit 0 in MRB of DTC 6 CMFA 0 R W Compare match Flag A Setting condition When TCNT TCORA Clearing condition Read CMFA when CMFA 1 the...

Page 287: ...ese bits specify how the timer output level is to be changed by a compare match A of TCORA and TCNT 00 No change when compare match A occurs 01 0 is output when compare match A occurs 10 1 is output when compare match A occurs 11 Output is inverted when compare match A occurs toggle output Note Only a 0 can be written to this bit to clear the flag 11 4 Operation 11 4 1 Pulse Output Figure 11 2 sho...

Page 288: ... Figure 11 4 shows the TCNT incrementation timing with external clock source The pulse width of the external clock for incrementation at signal edge must be at least 1 5 system clock φ periods and at least 2 5 states for incrementation at both edges The counter will not increment correctly if the pulse width is less than these values φ Internal clock TCNT input clock TCNT N 1 N N 1 Figure 11 3 Cou...

Page 289: ...t to 1 by a compare match signal generated when the TCOR and TCNT values match The compare match signal is generated at the last state in which the match is true just before the timer counter is updated Therefore when TCOR and TCNT match the compare match signal is not generated until the next incrementation clock input Figure 11 5 shows the timing of CMF flag setting φ Compare match A signal Time...

Page 290: ...1 5 4 Timing of Compare Match Clear When a Compare Match Occurs TCNT is cleared when compare match A or B occurs depending on the setting of the CCLR1 and CCLR0 bits in TCR Figure 11 7 shows the timing of this operation φ N H 00 Compare match signal TCNT Figure 11 7 Timing of Compare Match Clear 11 5 5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input dependi...

Page 291: ...and TCR_3 are set to B 100 the 8 bit timers of the two channels are cascaded With this configuration a single 16 bit timer can be used 16 bit timer mode or compare matches of 8 bit channel 0 Channel 2 can be counted by the timer of channel 1 Channel 3 compare match count mode In the case that channel 0 is connected to channel 1 in cascade the timer operates as described below 11 6 1 16 Bit Count M...

Page 292: ...utput from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8 bit compare match conditions 11 6 2 Compare Match Count Mode When bits CKS2 to CKS0 in TCR_1 are B 100 TCNT_1 counts compare match A for channel 0 Channels 0 and 1 are controlled independently Conditions such as setting of the CMF flag generation of interrupts output from the TMO pin and counter clearing are in ...

Page 293: ... Possible CMIB2 TCORA_2 compare match CMFB Possible OVI2 TCNT_2 overflow OVF Not possible CMIA3 TCORA_3 compare match CMFA Possible CMIB3 TCORA_3 compare match CMFB Possible OVI3 TCNT_3 overflow OVF Not possible Low 11 7 2 A D Converter Activation The A D converter can be activated only by channel 0 compare match A If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurren...

Page 294: ...write is not performed Figure 11 10 shows this operation φ Address TCNT address Internal write signal Counter clear signal TCNT N H 00 T1 T2 TCNT write cycle by CPU Figure 11 10 Conflict between TCNT Write and Clear 11 8 2 Conflict between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the write takes priority and the counter is not i...

Page 295: ...lict between TCOR Write and Compare Match During the T2 state of a TCOR write cycle the TCOR write has priority even if a compare match occurs and the compare match signal is disabled Figure 11 12 shows this operation φ Address TCOR address Internal write signal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N 1 Compare match signal Inhibited Figure 11 12 Conflict between TCOR Write...

Page 296: ...ration TCNT may increment erroneously when the internal clock is switched over Table 11 4 shows the relationship between the timing at which the internal clock is switched by writing to the CKS1 and CKS0 bits and the TCNT operation When the TCNT clock is generated from an internal clock the falling edge of the internal clock pulse is detected If clock switching causes a change from high to low lev...

Page 297: ...of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation 1 Switching from low to low 1 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit rewrite N N 1 2 Switching from low to high 2 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit rewrite N N 1 N 2 ...

Page 298: ... switching from high to stop 4 Generated on the assumption that the switchover is a falling edge TCNT is incremented 11 8 6 Conflict between Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested it will not be possible to clear the CPU interrupt source or the DTC activation source Interrupts should therefore be disabled before entering module stop mode...

Page 299: ...utputs are divided into 4 bit groups group 2 and group 3 that can operate both simultaneously and independently The block diagram of the PPG is shown in figure 12 1 12 1 Features 8 bit output data Two output groups Selectable output trigger signals Non overlap mode Can operate in tandem with the data transfer controller DTC Settable inverted output Module stop mode can be set PPG0000A_000020020300...

Page 300: ...ter H Next data enable register L Next data register H Next data register L Output data register H Output data register L PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL Pulse output pins group 3 Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 PODRH PODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Internal data bus Figure 12 1 Block Diagram of PPG ...

Page 301: ...12 Output Group 3 pulse output PO11 Output PO10 Output PO9 Output PO8 Output Group 2 pulse output 12 3 Register Descriptions The PPG has the following registers PPG output control register PCR PPG output mode register PMR Next data enable register H NDERH Next data enable register L NDERL Output data register H PODRH Output data register L PODRL Next data register H NDRH Next data register L NDRL ...

Page 302: ... W R W Next Data Enable 8 to 15 When a bit is set to 1 for pulse output by NDRH the value in the corresponding NDRH bit is transferred to the PODRH bit by the selected output trigger Values are not transferred from NDRH to PODRH for cleared bits NDERL Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R...

Page 303: ...pulse output by NDERH the output trigger transfers NDRH values to this register during PPG operation While NDERH is set to 1 the CPU cannot write to this register While NDERH is cleared the initial output value of the pulse can be set PODRL Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Output Data ...

Page 304: ...R15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Next Data Register 8 to 15 The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR If pulse output groups 2 and output pulse groups 3 have different output triggers the upper 4 bits and the lower 4 bits are mapped to different addresses as shown below B...

Page 305: ... W Description 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Next Data Register 0 to 7 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR If pulse output groups 0 and output pulse groups 1 have different output triggers upper 4 bits and lower 4 bits are mapped to the different addr...

Page 306: ...n output trigger selection refer to section 12 3 5 PPG Output Mode Register PMR Bit Bit Name Initial Value R W Description 7 6 G3CMS1 G3CMS0 1 1 R W R W Group 3 Compare Match Select 0 and 1 Select output trigger of pulse output group 3 00 Compare match in TPU channel 0 01 Compare match in TPU channel 1 10 Compare match in TPU channel 2 11 Compare match in TPU channel 3 5 4 G2CMS1 G2CMS0 1 1 R W R ...

Page 307: ...utput for pulse output group 3 0 Inverted output 1 Direct output 6 G2INV 1 R W Group 2 Inversion Selects direct output or inverted output for pulse output group 2 0 Inverted output 1 Direct output 5 4 All 1 R W Reserved 3 G3NOV 0 R W Group 3 Non Overlap Selects normal or non overlapping operation for pulse output group 3 0 Normal operation output values updated at compare match A in the selected T...

Page 308: ...responding PODR initial setting When the compare match event specified by PCR occurs the corresponding NDR bit contents are transferred to PODR to update the output values The sequential output of up to 8 bits of data is possible by writing new output data to NDR before the next compare match Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q N...

Page 309: ...ODR and output when the specified compare match event occurs Figure 12 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A TCNT N N 1 φ TGRA N Compare match A signal NDRH m n PODRH PO8 to PO15 n m n Figure 12 3 Timing of Transfer and Output of NDR Contents Example ...

Page 310: ...output compare register with output disabled 2 Set the PPG output trigger period 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used for pulse output...

Page 311: ...mpare match A Set the TGIEA bit of TIER to 1 to enable the compare match input capture A TGIA interrupt 2 Write H F8 in P1DDR and NDERH and set the G3CMS0 G3CMS1 G2CMS0 and G2CMS1 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger Write output data H 80 in NDRH 3 When compare match A occurs the NDRH contents are transferred to PODRH and outp...

Page 312: ...t pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D DDR Figure 12 6 Non Overlapping Pulse Output Therefore 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A The NDR contents should not be altered during the interval between compare match B and compare match A the non overlap margin This can be accomplished by having the TGI...

Page 313: ... 0 output 0 1 output 0 output Do not write to NDR here Write to NDR here Compare match A Compare match B NDR PODR Do not write to NDR here Write to NDR here Write to NDR Write to NDR Figure 12 7 Non Overlapping Operation and NDR Write Timing ...

Page 314: ...ut disabled 2 Set the pulse output trigger period in TGRB and the non overlap margin in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used for ...

Page 315: ... 12 9 shows an example in which pulse output is used for four phase complementary non overlapping pulse output TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non overlap margin Figure 12 9 Non Overlapping Pulse Output Example Four Phase Complementary ...

Page 316: ...e the output trigger Set the G3NOV and G2NOV bits in PMR to 1 to select non overlapping output Write output data H 95 in NDRH 3 The timer counter in the TPU channel starts When a compare match with TGRB occurs outputs change from 1 to 0 When a compare match with TGRA occurs outputs change from 0 to 1 the change from 0 to 1 is delayed by the value set in TGRA The TGIA interrupt handling routine wri...

Page 317: ...he inverse of the PODR contents can be output Figure 12 10 shows the outputs when G3INV and G2INV are cleared to 0 in addition to the settings of figure 12 9 TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 12 10 Inverted Pulse Output Example ...

Page 318: ...top Mode Setting PPG operation can be disabled or enabled using the module stop control register The initial setting is for PPG operation to be halted Register access is enabled by clearing module stop mode For details refer to section 21 Power Down Modes 12 5 2 Operation of Pulse Output Pins Pins PO8 to PO15 are also used for other peripheral functions such as the TPU When output by another perip...

Page 319: ...Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows it is possible to select whether this LSI is internally reset or not In interval timer mode If the counter overflows the WDT generates an interval timer interrupt WOVI Overflow Interrupt control WOVI interrupt request signal Internal reset signal Reset control RSTCSR TCNT TSCR φ 2 φ 64 φ ...

Page 320: ... Control Status Register TCSR TCSR is an 8 bit readable writable register Its functions include selecting the clock source to be input to TCNT and selecting the timer mode Bit Bit Name Initial Value R W Description 7 OVF 0 R W Overflow Flag Indicates that TCNT has overflowed Only a write of 0 is permitted to clear the flag Setting condition When TCNT overflows changes from H FF to H 00 When intern...

Page 321: ...ed 2 1 0 CKS2 CKS1 CKS0 0 0 0 R W R W R W Clock Select 0 to 2 Selects the clock source to be input to TCNT The overflow frequency for φ 20 MHz is enclosed in parentheses 000 Clock φ 2 frequency 25 6 µs 001 Clock φ 64 frequency 819 2 µs 010 Clock φ 128 frequency 1 6 ms 011 Clock φ 512 frequency 6 6 ms 100 Clock φ 2048 frequency 26 2 ms 101 Clock φ 8192 frequency 104 9 ms 110 Clock φ 32768 frequency...

Page 322: ... be written Setting condition Set when TCNT overflows changed from H FF to H 00 in watchdog timer mode Clearing condition Cleared by reading RSTCSR when WOVF 1 and then writing 0 to WOVF 6 RSTE 0 R W Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows during watchdog timer operation 0 Reset signal is not generated even if TCNT overflows Though this LSI i...

Page 323: ... for 518 states If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow the reset by the RES pin has priority and the WOVF bit in RSTCSR is cleared to 0 TCNT value H 00 Time H FF WT 1 TME 1 Write H 00 to TCNT WT 1 TME 1 Write H 00 to TCNT 518 states Internal reset signal WT TME Note The internal reset signal is generated only if the RSTE bit i...

Page 324: ...be written to by a byte transfer instruction TCNT and TCSR both have the same write address Therefore the relative condition shown in figure 13 3 needs to be satisfied in order to write to TCNT or TCSR The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition To write to RSTCSR execute a word transfer instruction for address H FF76 A byte transfer ins...

Page 325: ...e read in the same way as other registers The read addresses are H FF74 for TCSR H FF75 for TCNT and H FF77 for RSTCSR 13 5 2 Conflict between Timer Counter TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the write takes priority and the timer counter is not incremented Figure 13 4 shows this operation Address φ Internal write signal T...

Page 326: ...ot reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation however TCNT and TCSR of the WDT are reset TCNT TCSR or RSTCR cannot be written to for 132 states following an overflow During this period any attempt to read the WOVF flag is not acknowledged Accordingly wait 132 states after overflow to write 0 to the WOVF flag for clearing 13 5 6 OVF Flag Cl...

Page 327: ...bility The transmitter and receiver are mutually independent enabling transmission and reception to be executed simultaneously Double buffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data On chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source except for in...

Page 328: ... both supported RxD TxD SCK Clock External clock φ φ 4 φ 16 φ 64 TEI TXI RXI ERI RSR RDR TSR TDR SMR SCR SSR SCMR BRR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Smart card mode register Bit rate register SCMR SSR SCR SMR Transmission reception control Baud rate generator BRR Module ...

Page 329: ...used in the text for all channels omitting the channel designation 14 3 Register Descriptions The SCI has the following registers for each channel The serial mode register SMR serial status register SSR and serial control register SCR are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions differ in part Receive Shift Regist...

Page 330: ...not be written to by the CPU 14 3 3 Transmit Data Register TDR TDR is an 8 bit register that stores data for transmission When the SCI detects that TSR is empty it transfers the transmit data written in TDR to TSR and starts transmission The double buffered structure of TDR and TSR enables continuous serial transmission If the next transmit data has already been written to TDR during serial transm...

Page 331: ...d and the MSB of TDR is not transmitted in transmission In clocked synchronous mode a fixed data length of 8 bits is used 5 PE 0 R W Parity Enable enabled only in asynchronous mode When this bit is set to 1 the parity bit is added to transmit data before transmission and the parity bit is checked in reception For a multiprocessor format parity bit addition and checking are not performed regardless...

Page 332: ...t settings are invalid in multiprocessor mode 1 0 CKS1 CKS0 0 0 R W R W Clock Select 0 and 1 These bits select the clock source for the baud rate generator 00 φ clock n 0 01 φ 4 clock n 1 10 φ 16 clock n 2 11 φ 64 clock n 3 For the relationship between the bit rate register setting and the baud rate see section 14 3 9 Bit Rate Register BRR n is the decimal representation of the value of n in BRR s...

Page 333: ...this bit is set to 1 the parity bit is added to transmit data in transmission and the parity bit is checked in reception In Smart Card interface mode this bit must be set to 1 4 O E 0 R W Parity Mode enabled only when the PE bit is 1 in asynchronous mode 0 Selects even parity 1 Selects odd parity For details on setting this bit in Smart Card interface mode refer to section 14 7 2 Data Format Excep...

Page 334: ...elect the clock source for the baud rate generator 00 φ clock n 0 01 φ 4 clock n 1 10 φ 16 clock n 2 11 φ 64 clock n 3 For the relationship between the bit rate register setting and the baud rate see section 14 3 9 Bit Rate Register BRR n is the decimal representation of the value of n in BRR see section 14 3 9 Bit Rate Register BRR ...

Page 335: ...d 6 RIE 0 R W Receive Interrupt Enable When this bit is set to 1 RXI and ERI interrupt requests are enabled 5 TE 0 R W Transmit Enable When this bit s set to 1 transmission is enabled 4 RE 0 R W Receive Enable When this bit is set to 1 reception is enabled 3 MPIE 0 R W Multiprocessor Interrupt Enable enabled only when the MP bit in SMR is 1 in asynchronous mode When this bit is set to 1 receive da...

Page 336: ...nal baud rate generator SCK pin functions as I O port 01 Internal baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK pin 1X External clock Inputs a clock with a frequency 16 times the bit rate from the SCK pin Clocked synchronous mode 0X Internal clock SCK pin functions as clock output 1X External clock SCK pin functions as clock input Legend X Don t care ...

Page 337: ... R W Multiprocessor Interrupt Enable enabled only when the MP bit in SMR is 1 in asynchronous mode Write 0 to this bit in Smart Card interface mode 2 TEIE 0 R W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode 1 0 CKE1 CKE0 0 0 R W R W Clock Enable 0 and 1 Enables or disables clock output from the SCK pin The clock output can be dynamically switched in GSM mode For de...

Page 338: ...contains transmit data Setting conditions When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DTC is activated by a TXI interrupt request and writes data to TDR 6 RDRF 0 R W Receive Data Register Full Indicates that the received data is stored in RDR Setting condition When se...

Page 339: ...is written to FER after reading FER 1 In 2 stop bit mode only the first stop bit is checked 3 PER 0 R W Parity Error Setting condition When a parity error is detected during reception Clearing condition When 0 is written to PER after reading PER 1 2 TEND 1 R Transmit End Setting conditions When the TE bit in SCR is 0 When TDRE 1 at transmission of the last bit of a 1 byte serial transmit character...

Page 340: ...it data Setting conditions When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DTC is activated by a TXI interrupt request and writes data to TDR 6 RDRF 0 R W Receive Data Register Full Indicates that the received data is stored in RDR Setting condition When serial reception ...

Page 341: ...ing condition When 0 is written to ORER after reading ORER 1 4 ERS 0 R W Error Signal Status Setting condition When the low level of the error signal is sampled Clearing conditions When 0 is written to ERS after reading ERS 1 3 PER 0 R W Parity Error Setting condition When a parity error is detected during reception Clearing condition When 0 is written to PER after reading PER 1 ...

Page 342: ...of 1 byte data The timing of bit setting differs according to the register setting as follows When GM 0 and BLK 0 2 5 etu after transmission starts When GM 0 and BLK 1 1 5 etu after transmission starts When GM 1 and BLK 0 1 0 etu after transmission starts When GM 1 and BLK 1 1 0 etu after transmission starts Clearing conditions When 0 is written to TDRE after reading TDRE 1 When the DTC is activat...

Page 343: ...r 7 bit data LSB first is fixed 2 SINV 0 R W Smart Card Data Invert Specifies inversion of the data logic level The SINV bit does not affect the logic level of the parity bit To invert the parity bit invert the O E bit in SMR 0 TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form...

Page 344: ...rface Mode N S 2 2n 1 B φ 106 1 Error B S 2 2n 1 N 1 1 100 φ 106 Note B Bit rate bit s N BRR setting for baud rate generator 0 N 255 φ Operating frequency MHz n and S Determined by the SMR settings shown in the following tables SMR Setting SMR Setting CKS1 CKS0 n BCP1 BCP0 S 0 0 0 0 0 32 0 1 1 0 1 64 1 0 2 1 0 372 1 1 3 1 1 256 Table 14 3 shows sample N settings in BRR in normal asynchronous mode ...

Page 345: ...73 19200 0 7 0 00 0 7 1 73 31250 0 3 0 00 0 4 1 70 0 4 0 00 38400 0 3 0 00 0 3 1 73 Operating Frequency φ φ φ φ MHz 6 6 144 7 3728 8 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 106 0 44 2 108 0 08 2 130 0 07 2 141 0 03 150 2 77 0 16 2 79 0 00 2 95 0 00 2 103 0 16 300 1 155 0 16 1 159 0 00 1 191 0 00 1 207 0 16 600 1 77 0 16 1 79 0 00 1 95 0 00 1 103 0 16 1200 0 155 0 16 0 159 0 00...

Page 346: ...38 0 16 0 39 0 00 19200 0 15 0 00 0 15 1 73 0 19 2 34 0 19 0 00 31250 0 9 1 70 0 9 0 00 0 11 0 00 0 11 2 40 38400 0 7 0 00 0 7 1 73 0 9 2 34 0 9 0 00 Operating Frequency φ φ φ φ MHz 14 14 7456 16 17 2032 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 248 0 17 3 64 0 70 3 70 0 03 3 75 0 48 150 2 181 0 13 2 191 0 00 2 207 0 13 2 223 0 00 300 2 90 0 13 2 95 0 00 2 103 0 13 2 111 0 00 60...

Page 347: ...77 0 16 4800 0 116 0 16 0 127 0 00 0 129 0 16 0 155 0 16 9600 0 58 0 69 0 63 0 00 0 64 0 16 0 77 0 16 19200 0 28 1 02 0 31 0 00 0 32 1 36 0 38 0 16 31250 0 17 0 00 0 19 1 70 0 19 0 00 0 23 0 38400 0 14 2 34 0 15 0 00 0 15 1 73 0 19 2 34 Table 14 4 Maximum Bit Rate for Each Frequency Asynchronous Mode φ φ φ φ MHz Maximum Bit Rate bit s n N φ φ φ φ MHz Maximum Bit Rate bit s n N 4 125000 0 0 12 3750...

Page 348: ...nput Clock MHz Maximum Bit Rate bit s 4 1 0000 62500 12 3 0000 187500 4 9152 1 2288 76800 12 288 3 0720 192000 5 1 2500 78125 14 3 5000 218750 6 1 5000 93750 14 7456 3 6864 230400 6 144 1 5360 96000 16 4 0000 250000 7 3728 1 8432 115200 17 2032 4 3008 268800 8 2 0000 125000 18 4 5000 281250 9 8304 2 4576 153600 19 6608 4 9152 307200 10 2 5000 156250 20 5 0000 312500 24 6 0000 375000 ...

Page 349: ...00k 0 9 0 19 0 24 0 39 0 49 0 59 250k 0 3 0 7 0 9 0 15 0 19 0 23 500k 0 1 0 3 0 4 0 7 0 9 0 11 1M 0 0 0 1 0 3 0 4 0 5 2 5M 0 0 0 1 5M 0 0 Legend Blank Setting prohibited Can be set but there will be a degree of error Continuous transfer is not possible Table 14 7 Maximum Bit Rate with External Clock Input Clocked Synchronous Mode φ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bit s φ φ φ φ ...

Page 350: ...ting Frequency φ φ φ φ MHz 14 2848 16 00 18 00 20 00 24 00 Bit Rate bit s n N Error n N Error n N Error n N Error n N Error 9600 0 1 0 00 0 1 12 01 0 2 15 99 0 2 6 60 0 2 12 01 Table 14 9 Maximum Bit Rate at Various Frequencies Smart Card Interface Mode when S 372 φ φ φ φ MHz Maximum Bit Rate bit s n N φ φ φ φ MHz Maximum Bit Rate bit s n N 7 1424 9600 0 0 14 2848 19200 0 0 10 00 13441 0 0 16 00 2...

Page 351: ...tate low level recognizes a start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex Both the transmitter and the receiver also have a double buffered structure so data can be read or written during transmission or reception enabling continuous data transfer LSB Start bit MSB Idle state mark state Stop bit 0 Transmit receive d...

Page 352: ... S 8 bit data MPB STOP S 8 bit data MPB STOPSTOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 SMR Settings 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transfer Format and Frame Length STOP S 8 bit data P STOP S 7 bit data STOP P STOP Legend S Start bit STOP Stop bit P Parity bit MPB Multiprocessor ...

Page 353: ...de is given by formula 1 below M 0 5 L 0 5 F 100 1 2N D 0 5 N Formula 1 Where N Ratio of bit rate to clock N 16 D Clock duty cycle D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F absolute value of clock rate deviation 0 and D clock duty cycle 0 5 in formula 1 the reception margin can be given by the formula M 0 5 1 2 16 100 46 875 However this is...

Page 354: ...ock is input at the SCK pin the clock frequency should be 16 times the bit rate used When the SCI is operated on an internal clock the clock can be output from the SCK pin The frequency of the clock output in this case is equal to the bit rate and the phase is such that the rising edge of the clock is in the middle of the transmit data as shown in figure 14 4 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1 ...

Page 355: ...tion completion Start initialization Set data transfer format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE and RE bits are cleared to 0 No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits 4 1 bit interval elapsed 1 Set the clock selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When ...

Page 356: ...t or multiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE flag is 0 the data is transferred from TDR to TSR the stop bit is sent and then serial transmission of the next frame is started 6 If the TDRE flag is 1 the TEND flag in SSR is set to 1 the stop bit is sent and then the mark state is entere...

Page 357: ...mit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when the DTC is activated ...

Page 358: ...o 1 at this time an ERI interrupt request is generated 4 If a framing error is detected when the stop bit is 0 the FER bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 5 If reception is completed successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR ...

Page 359: ...ing reception Figure 14 9 shows a sample flow chart for serial data reception Table 14 11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error framing error 1 1 0 1 Lost Overrun error parity error 0 0 1 1 Tran...

Page 360: ... that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the input port corresponding to the RxD pin 4 SCI status check and receive data read Read SSR and check that RDRF 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF fl...

Page 361: ...sing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0 Figure 14 9 Sample Serial Reception Data Flowchart 2 ...

Page 362: ...th which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receives the data sent next Stations whose IDs do not match continue to skip data until data with...

Page 363: ... 03 ID 04 Serial transmission line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 14 10 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A ...

Page 364: ...s automatically designated as the transmit data output pin After the TE bit is set to 1 a frame of 1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial tran...

Page 365: ... bit Stop bit Start bit Data Data2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine If not this station s ID MPIE bit is set to 1 again RXI interrupt request is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D7 0...

Page 366: ... and check that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 4 SCI status check and data reception Read SSR and check that the RDRF flag is set to 1 then read the data in RDR 5 Receive error proc...

Page 367: ...rror processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 14 13 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 368: ...munication through the use of a common clock Both the transmitter and the receiver also have a double buffered structure so data can be read or written during transmission or reception enabling continuous data transfer Don t care Don t care One unit of transfer data character or frame Bit 0 Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note High except in cont...

Page 369: ...ion Set data transfer format in SMR and SCMR No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits 4 1 bit interval elapsed Set CKE1 and CKE0 bits in SCR TE RE bits 0 1 1 Set the clock selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE TE and RE to 0 2 Set the data transfer format in SMR and SCMR 3 Write a value cor...

Page 370: ... specified 4 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 5 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the next frame is started 6 If the TDRE flag is set to 1 the TEND flag in SSR is set to 1 and the TDRE flag maintains the output state of the last bit If the TEIE bit in SCR is set to 1 at this time a TEI interrupt reque...

Page 371: ... status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is au...

Page 372: ...If reception is completed successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated Continuous reception is possible because the RXI interrupt routine reads the receive data transferred to RDR before reception of the next receive data has finished Bit 7 Serial data Synchronization clock 1...

Page 373: ...orming the appropriate error processing clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 5 Serial reception continuation procedure ...

Page 374: ...CI To switch from transmit mode to simultaneous transmit and receive mode after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1 clear TE to 0 Then simultaneously set TE and RE to 1 with a single instruction To switch from receive mode to simultaneous transmit and receive mode after checking that the SCI has finished reception clear RE to 0 Then after checki...

Page 375: ...ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt 5 Serial transmission reception continuation procedure To continue serial transmission reception before the MSB bit 7 of the current frame is...

Page 376: ...eception are carried out on a single data transmission line the TxD pin and RxD pin should be connected to the LSI pin The data transmission line should be pulled up to the VCC power supply with a resistor If an IC card is not connected and the TE and RE bits are both set to 1 closed transmission reception is possible enabling self diagnosis to be carried out When the clock generated on the Smart ...

Page 377: ...after the start bit If an error signal is sampled during transmission the same data is retransmitted automatically after a delay of 2 etu or longer Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error occurs Transmitting station output DE Receiving station output Start bit Data bits Parity bit Error signal Legend ...

Page 378: ...g to Smart Card regulations even parity mode is the logic 0 level of the parity bit and corresponds to state Z In this LSI the SINV bit inverts only data bits D0 to D7 Therefore set the O E bit in SMR to 1 to invert the parity bit for both transmission and reception 14 7 3 Block Transfer Mode Operation in block transfer mode is the same as that in SCI asynchronous mode except for the following poi...

Page 379: ...nd 186th or 128th pulse of the basic clock data can be latched at the middle of the bit The reception margin is given by the following formula M 0 5 L 0 5 F 1 F 100 1 2N D 0 5 N Where M Reception margin N Ratio of bit rate to clock N 32 64 372 and 256 D Clock duty cycle D 0 to 1 0 L Frame length L 10 F Absolute value of clock frequency deviation Assuming values of F 0 D 0 5 and N 372 in the above ...

Page 380: ...ceive mode after checking that the SCI has finished transmission initialize the SCI and set TE to 0 and RE to 1 Whether SCI has finished transmission or not can be checked with the TEND flag 14 7 6 Data Transmission Except for Block Transfer Mode As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing the operations are different from those in...

Page 381: ...this period the TEND flag remains cleared to 0 and the DTC is not activated Therefore the SCI and DTC will automatically transmit the specified number of bytes in the event of an error including retransmission However the ERS flag is not cleared automatically when an error occurs and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error and ...

Page 382: ...t in SMR The TEND flag set timing is shown in figure 14 27 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I O data 12 5etu TXI TEND interrupt 11 0etu DE Guard time When GM 0 When GM 1 Start bit Data bits Parity bit Error signal Legend Ds D0 to D7 Dp DE Figure 14 27 TEND Flag Generation Timing in Transmission Operation ...

Page 383: ...ear TE bit to 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND 1 All data transmitted TEND 1 ERS 0 ERS 0 Figure 14 28 Example of Transmission Processing Flow ...

Page 384: ...cally by specifying the DTC to be activated using an RXI interrupt source In a receive operation an RXI interrupt request is generated when the RDRF flag in SSR is set to 1 If the RXI request is designated beforehand as a DTC activation source the DTC will be activated by the RXI request and the receive data will be transferred The RDRF flag is cleared to 0 automatically when data is transferred b...

Page 385: ...w 14 7 8 Clock Output Control When the GM bit in SMR is set to 1 the clock output level can be fixed with bits CKE0 and CKE1 in SCR At this time the minimum clock pulse width can be made the specified width Figure 14 31 shows the timing for fixing the clock output level In this example GM is set to 1 CKE1 is cleared to 0 and the CKE0 bit is controlled Specified pulse width SCK CKE0 Specified pulse...

Page 386: ...data register DR and data direction register DDR corresponding to the SCK pin to the value for the fixed output state in software standby mode 2 Write 0 to the TE bit and RE bit in the serial control register SCR to halt transmit receive operation At the same time set the CKE1 bit to the value for the fixed output state in software standby mode 3 Write 0 to the CKE0 bit in SCR to halt the clock 4 ...

Page 387: ...set to 1 an ERI interrupt request is generated An RXI interrupt request can activate the DTC to transfer data The RDRF flag is cleared to 0 automatically when data is transferred by the DTC A TEI interrupt is requested when the TEND flag is set to 1 and the TEIE bit is set to 1 If a TEI interrupt and a TXI interrupt are requested simultaneously the TXI interrupt has priority for acceptance However...

Page 388: ...hen data is transferred by the DTC In the event of an error the SCI retransmits the same data automatically During this period the TEND flag remains cleared to 0 and the DTC is not activated Therefore the SCI and DTC will automatically transmit the specified number of bytes in the event of an error including retransmission However the ERS flag is not cleared automatically when an error occurs Henc...

Page 389: ...tion input or output and level are determined by DR and DDR This can be used to set the TxD pin to mark state high level or send a break during serial data transmission To maintain the communication line at mark state until TE is set to 1 set both DDR and DR to 1 As TE is cleared to 0 at this point the TxD pin becomes an I O port and 1 is output from the TxD pin To send a break during serial trans...

Page 390: ...Rev 1 0 09 02 page 354 of 568 ...

Page 391: ... serial communication Communication speed Max 1 Mbps Data length 0 to 8 bytes Number of channels 1 Data buffers 16 one receive only buffer and 15 buffers settable for transmission reception Data transmission Two methods Mailbox buffer number order low to high Message priority identifier reverse order high to low Data reception Two methods Message identifier match transmit receive setting buffers R...

Page 392: ...rface MBI The MBI consisting of mailboxes and a local acceptance filter mask LAFM stores CAN transmit receive messages identifiers data etc Transmit messages are written by the CPU For receive messages the data received by the CDLC is stored automatically Microprocessor Interface MPI The MPI consisting of a bus interface control register status register etc controls HCAN internal data status and s...

Page 393: ...Descriptions The HCAN has the following registers Master control register MCR General status register GSR Bit configuration register BCR Mailbox configuration register MBCR Transmit wait register TXPR Transmit wait cancel register TXCR Transmit acknowledge register TXACK Abort acknowledge register ABACK Receive complete register RXPR Remote request register RFPR Interrupt register IRR Mailbox inte...

Page 394: ...ue should always be 0 5 MCR5 0 R W HCAN Sleep Mode When this bit is set to 1 the HCAN transits to HCAN sleep mode When this bit is cleared to 0 HCAN sleep mode is released 4 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 MCR2 0 R W Message Transmission Method 0 Transmission order determined by message identifier priority 1 Transmission order determined by m...

Page 395: ...SR GSR is an 8 bit register that indicates the status of the CAN bus Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 GSR3 1 R Reset Status Bit Indicates whether the HCAN module is in the normal operation state or the reset state This bit cannot be modified Setting condition When entering configuration mode afte...

Page 396: ...ified Setting condition Start of message transmission SOF Clearing condition Interval of three bits after EOF End of Frame 1 GSR1 0 R Transmit Receive Warning Flag This bit cannot be modified Clearing condition When TEC 96 and REC 96 or TEC 256 Setting condition When TEC 96 or REC 96 0 GSR0 0 R Bus Off Flag This bit cannot be modified Setting condition When TEC 256 bus off state Clearing condition...

Page 397: ...5 BCR4 BCR3 BCR2 BCR1 BCR0 0 0 0 0 0 0 R W R W R W R W R W R W Baud Rate Prescaler BRP Set the length of time quanta 000000 2 system clock 000001 4 system clock 000010 6 system clock 111111 128 system clock 7 BCR15 0 R W Bit Sample Point BSP Sets the point at which data is sampled 0 Bit sampling at one point end of time segment 1 TSEG1 1 Bit sampling at three points end of TSEG1 and preceding and ...

Page 398: ...PHSEG1 width to between 4 and 16 time quanta 0000 Setting prohibited 0001 Setting prohibited 0010 Setting prohibited 0011 4 time quanta 0100 5 time quanta 0101 6 time quanta 0110 7 time quanta 0111 8 time quanta 1000 9 time quanta 1001 10 time quanta 1010 11 time quanta 1011 12 time quanta 1100 13 time quanta 1101 14 time quanta 1110 15 time quanta 1111 16 time quanta ...

Page 399: ...CR2 MBCR1 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R R W R W R W R W R W R W R W R W These bits set the transfer direction for the corresponding mailboxes 1 to 15 MBCRn determines the transfer direction for mailbox n n 1 to 15 0 Corresponding mailbox is set for transmission 1 Corresponding mailbox is set for reception Bit 8 i...

Page 400: ...XPR2 TXPR1 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R R W R W R W R W R W R W R W R W These bits set a transmit wait CAN bus arbitration wait for the corresponding mailboxes 1 to 15 When TXPRn n 1 to 15 is set to 1 the message in mailbox n becomes the transmit wait state Clearing condition Completion of message transmission C...

Page 401: ... TXCR1 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R R W R W R W R W R W R W R W R W These bits cancel the transmit wait message in the corresponding mailboxes 1 to 15 When TXCRn n 1 to 15 is set to 1 the transmit wait message in mailbox n is canceled Clearing condition Completion of TXPR clearing when transmit message is cancel...

Page 402: ...TXACK10 TXACK9 TXACK8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R R W R W R W R W R W R W R W R W These bits are status flags that indicate error free transmission of the transmit message in the corresponding mailboxes 1 to 15 When the message in mailbox n n 1 to 15 has been transmitted error free TXACKn is set to 1 Setting condition Completion of message transmission for corresp...

Page 403: ...10 ABACK9 ABACK8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R R W R W R W R W R W R W R W R W These bits are status flags that indicate error free cancellation abortion of the transmit message in the corresponding mailboxes 1 to 15 When the message in mailbox n n 1 to 15 has been canceled error free ABACKn is set to 1 Setting condition Completion of transmit message cancellation f...

Page 404: ... Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W When the message in mailbox n n 1 to 15 has been received error free RXPRn is set to 1 Setting condition Completion of m...

Page 405: ... Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W When mailbox n n 0 to 15 has received the remote frame error free RFPRn n 1 to 15 is set to 1 Setting condition Completion of re...

Page 406: ...n error active passive state Clearing condition Writing 1 14 IRR6 0 R W Bus Off Interrupt Flag Status flag indicating the bus off state caused by the transmit error counter Setting condition When TEC 256 Clearing condition Writing 1 13 IRR5 0 R W Error Passive Interrupt Flag Status flag indicating the error passive state caused by the transmit receive error counter Setting condition When TEC 128 o...

Page 407: ...en TEC 96 Clearing condition Writing 1 10 IRR2 0 R Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been received in a mailbox buffer Setting condition When remote frame reception is completed when corresponding MBIMR 0 Clearing condition Clearing of all bits in RFPR remote request register 9 IRR1 0 R Receive Message Interrupt Flag Status flag indicating that a ma...

Page 408: ...ller enables interrupts Setting condition When the reset operation has finished after entering power on reset or software standby mode Clearing condition Writing 1 7 to 5 All 0 Reserved These bits are always read as 0 The write value should always be 0 4 IRR12 0 R W Bus Operation Interrupt Flag Status flag indicating detection of a dominant bit due to bus operation when the HCAN module is in HCAN ...

Page 409: ...age status register is set Clearing condition Clearing of all bits in UMSR unread message status register 0 IRR8 0 R W Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox Setting condition When TXPR transmit wait register is cleared by completion of transmission or completion of transmission abort Clearing condition Writing 1 Note Only 1 ...

Page 410: ...MR1 MBIMR0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Mailbox Interrupt Mask MBIMRx When MBIMRn n 1 to 15 is cleared to 0 the interrupt request in mailbox n is enabled When set to 1 the interrupt request is masked The interrupt source in a transmit mailbox is TXPR clearing caused by t...

Page 411: ...est by IRR5 ERS0 is enabled When set to 1 it is masked 12 IMR4 1 R W Receive Overload Warning Interrupt Mask When this bit is cleared to 0 an interrupt request by IRR4 OVR0 is enabled When set to 1 it is masked 11 IMR3 1 R W Transmit Overload Warning Interrupt Mask When this bit is cleared to 0 an interrupt request by IRR3 OVR0 is enabled When set to 1 it is masked 10 IMR2 1 R W Remote Frame Reque...

Page 412: ... it is masked 0 IMR8 1 R W Mailbox Empty Interrupt Mask When this bit is cleared to 0 an interrupt request by IRR8 SLE0 is enabled When set to 1 it is masked 15 3 14 Receive Error Counter REC The receive error counter REC is an 8 bit read only register that functions as a counter indicating the number of receive message errors on the CAN bus The count value is stipulated in the CAN protocol 15 3 1...

Page 413: ...message is lost Bit Bit Name Initial Value R W Description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Setting condition When a new message is received before RXPR is cleared Clearing condition Writing 1 When...

Page 414: ...fier is not compared When this bit is set to 1 ID 4 of the receive message identifier is not compared When this bit is set to 1 ID 3 of the receive message identifier is not compared When this bit is set to 1 ID 2 of the receive message identifier is not compared When this bit is set to 1 ID 1 of the receive message identifier is not compared When this bit is set to 1 ID 0 of the receive message i...

Page 415: ...W When this bit is set to 1 ID 17 of the receive message identifier is not compared When this bit is set to 1 ID 16 of the receive message identifier is not compared When this bit is set to 1 ID 28 of the receive message identifier is not compared When this bit is set to 1 ID 27 of the receive message identifier is not compared When this bit is set to 1 ID 26 of the receive message identifier is n...

Page 416: ...MC0 3 MC1 3 MC2 3 MC3 3 MC15 3 MC0 4 MC1 4 MC2 4 MC3 4 MC15 4 MC0 5 MC1 5 MC2 5 MC3 5 MC15 5 MC0 6 MC1 6 MC2 6 MC3 6 MC15 6 MC0 7 MC1 7 MC2 7 MC3 7 MC15 7 MC0 8 MC1 8 MC2 8 MC3 8 MC15 8 Mail box 0 Mail box 1 Mail box 2 Mail box 3 Mail box 15 Figure 15 2 Message Control Register Configuration The setting of message control registers are shown in the following Figures 15 3 and 15 4 show the correspo...

Page 417: ...initialized by writing 0 or 1 7 to 5 ID 20 to ID 18 R W Sets ID 20 to ID 18 in the identifier 4 RTR R W Remote Transmission Request Used to distinguish between data frames and remote frames 0 Data frame 1 Remote frame 3 IDE R W Identifier Extension Used to distinguish between the standard format and extended format of data frames and remote frames 0 Standard format 1 Extended format 2 R W The init...

Page 418: ...for each mailbox MD0 1 MD1 1 MD2 1 MD3 1 MD15 1 MD0 2 MD1 2 MD2 2 MD3 2 MD15 2 MD0 3 MD1 3 MD2 3 MD3 3 MD15 3 MD0 4 MD1 4 MD2 4 MD3 4 MD15 4 MD0 5 MD1 5 MD2 5 MD3 5 MD15 5 MD0 6 MD1 6 MD2 6 MD3 6 MD15 6 MD0 7 MD1 7 MD2 7 MD3 7 MD15 7 MD0 8 MD1 8 MD2 8 MD3 8 MD15 8 Mail box 0 Mail box 1 Mail box 2 Mail box 3 Mail box 15 Figure 15 5 Message Data Configuration 15 3 20 HCAN Monitor Register HCANMON HC...

Page 419: ...R W HTxD Transmission Stop Controls transmission stop of the HTxD pin 0 Enables transmission from the HTxD pin 1 Fixes an output level of the HTxD pin at 1 and transmission is stopped 5 to 2 Undefined Reserved These bits are always read as undefined values and cannot be modified 1 TxD Undefined R Transmission pin The state of the HTxD pin is read This bit cannot be modified 0 RxD Undefined R Recep...

Page 420: ...15 4 2 Initialization after Hardware Reset After a hardware reset the following initialization processing should be carried out 1 Clearing of IRR0 bit in the interrupt register IRR 2 Bit rate setting 3 Mailbox transmit receive settings 4 Mailbox RAM initialization 5 Message transmission method setting These initial settings must be made while the HCAN is in bit configuration mode Configuration mod...

Page 421: ... Period in which BCR MBCR etc are initialized Settings by user Processing by hardware Initialization of HCAN module Clear IRR0 BCR setting MBCR setting Mailbox initialization Message transmission method initialization IMR setting interrupt mask setting MBIMR setting interrupt mask setting MC x setting receive identifier setting LAFM setting receive identifier mask setting Figure 15 6 Hardware Rese...

Page 422: ...ssage transmission method initialization OK IMR setting MBIMR setting MC x setting LAFM setting OK GSR3 0 11 recessive bits received Yes Yes Yes Figure 15 7 Software Reset Flowchart Bit Rate and Bit Timing Settings The bit rate and bit timing settings are made in the bit configuration register BCR Settings should be made such that all CAN controllers connected to the CAN bus have the same baud rat...

Page 423: ...on is established PHSEG2 is a buffer segment for correcting phase drift negative This segment is shortened when synchronization resynchronization is established Limits on the settable value TSEG1 TSEG2 BRP sample point and SJW are shown in table 15 2 Table 15 2 Limits for the Settable Value Name Abbreviation Min Value Max Value Time segment 1 TSEG1 B 0011 2 B 1111 Time segment 2 TSEG2 B 001 3 B 11...

Page 424: ...10 011 100 101 110 111 TSEG1 0011 No Yes No No No No No BCR11 BCR8 0100 Yes Yes Yes No No No No 0101 Yes Yes Yes Yes No No No 0110 Yes Yes Yes Yes Yes No No 0111 Yes Yes Yes Yes Yes Yes No 1000 Yes Yes Yes Yes Yes Yes Yes 1001 Yes Yes Yes Yes Yes Yes Yes 1010 Yes Yes Yes Yes Yes Yes Yes 1011 Yes Yes Yes Yes Yes Yes Yes 1100 Yes Yes Yes Yes Yes Yes Yes 1101 Yes Yes Yes Yes Yes Yes Yes 1110 Yes Yes ...

Page 425: ... priority Either of the message transmission methods can be selected with the message transmission method bit MCR2 in the master control register MCR When messages are set to be transmitted according to the message identifier priority if several messages are designated as waiting for transmission TXPR 1 the message with the highest priority in the message identifier is stored in the transmit buffe...

Page 426: ...etting MBCR setting Mailbox initialization Message transmission method setting Yes No Yes Yes Settings by user Processing by hardware No No Interrupt settings Transmit data setting Arbitration field setting Control field setting Data field setting Message transmission GSR2 0 during transmission only TXACK 1 IRR8 1 Clear TXACK Clear IRR8 Message transmission wait TXPR setting Bus idle Transmission ...

Page 427: ... transmit wait bit TXPR1 to TXPR15 in the transmit wait register TXPR is set to 1 after message control and message data registers have been set the message enters transmit wait state If the message is transmitted error free the corresponding acknowledge bit TXACK1 to TXACK15 in the transmit acknowledge register TXACK is set to 1 and the corresponding transmit wait bit TXPR1 to TXPR15 in the trans...

Page 428: ...uring data frame or remote frame transmission Figure 15 10 shows a flowchart for transmit message cancellation Message transmit wait TXPR setting Yes No Yes No Settings by user Processing by hardware Set TXCR bit corresponding to message to be canceled Message not sent Clear TXCR TXPR ABACK 1 IRR8 1 Clear TXACK Clear ABACK Clear IRR8 Completion of message transmission TXACK 1 Clear TXCR TXPR IRR8 ...

Page 429: ... BCR setting MBCR setting Mailbox RAM initialization Receive data setting Arbitration field setting Local acceptance filter settings Interrupt settings Message reception Match of identifier in mailbox Same RXPR 1 IMR1 1 Data frame Interrupt to CPU Clear IRR1 End of reception Clear IRR2 IRR1 Unread message No RXPR RFPR 1 IRR2 1 IRR1 1 Message control read Message data read Message control read Mess...

Page 430: ...0_1010 standard format and the LAFM setting is 000_0000_0011 0 Care 1 Don t Care a total of four kinds of message identifiers can be received by mailbox 0 Identifier 1 010_1010_1000 Identifier 2 010_1010_1001 Identifier 3 010_1010_1010 Identifier 4 010_1010_1011 Message reception When a message is received a CRC check is performed automatically If the result of the CRC check is normal ACK is trans...

Page 431: ...can be sent to the CPU according to the settings of the corresponding bit MBIMR0 to MBIMR15 in the mailbox interrupt mask register MBIMR and the remote frame request interrupt mask IRR2 in the interrupt mask register IMR Unread message overwrite If the receive message identifier matches the mailbox identifier the receive message is stored in the mailbox regardless of whether the mailbox contains a...

Page 432: ...r IRR9 Message control message data read Processing by hardware Yes Figure 15 12 Unread Message Overwrite Flowchart 15 4 5 HCAN Sleep Mode The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep state in order to reduce current consumption Figure 15 13 shows a flowchart of the HCAN sleep mode ...

Page 433: ... No No No Yes manual No automatic MCR5 1 Bus idle Initialize TEC and REC Bus operation Settings by user Processing by hardware No No IMR12 1 Sleep mode clearing method MCR7 0 11 recessive bits received CAN bus communication possible CPU interrupt Figure 15 13 HCAN Sleep Mode Flowchart ...

Page 434: ...aring by software HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU Clearing by CAN bus operation The cancellation method is selected by the MCR7 bit setting in MCR Clearing by CAN bus operation occurs automatically when the CAN bus performs an operation and this change is detected In this case the first message is not stored in a mailbox messages will be received normally from the se...

Page 435: ...he HCAN halt mode MCR1 1 Yes Settings by user Processing by hardware No Bus idle Set MBCR MCR1 0 CAN bus communication possible Figure 15 14 HCAN Halt Mode Flowchart HCAN halt mode is entered by setting the halt request bit MCR1 to 1 in the master control register MCR If the CAN bus is operating the transition to HCAN halt mode is delayed until the bus becomes idle HCAN halt mode is cleared by cle...

Page 436: ...t Flag DTC Activation Error passive interrupt TEC 128 or REC 128 IRR5 Bus off interrupt TEC 256 IRR6 Reset processing interrupt by power on reset IRR0 Remote frame reception IRR2 Error warning interrupt TEC 96 IRR3 Error warning interrupt REC 96 IRR4 Overload frame transmission interrupt IRR7 Unread message overwrite IRR9 ERS0 OVR0 Detection of CAN bus operation in HCAN sleep mode IRR12 Not possib...

Page 437: ...rrupt request is not sent to the CPU by a reception interrupt from the HCAN Figure 15 15 shows a DTC transfer flowchart DTC initialization DTC enable register setting DTC register information setting Yes Yes Settings by user Processing by hardware No No Message reception in HCAN s mailbox 0 Transfer counter 0 or DISEL 1 DTC activation End of DTC transfer RXPR and RFPR clearing Interrupt to CPU End...

Page 438: ...or details refer to section 21 Power Down Modes 15 8 2 Reset The HCAN is reset by a power on reset in hardware standby mode and in software standby mode All the registers are initialized by a reset however mailboxes message control MCx x message data MDx x are not initialized Mailboxes message control MCx x message data MDx x are initialized after power on and at this time their initial values are...

Page 439: ...of error active and error passive REC and TEC perform count up and down normally In the bus off state 11 bit recessive sequences are counted REC 1 using REC When REC reaches 96 during the count IRR4 and GSR1 are set 15 8 6 Register Access Byte or word access can be performed for all HCAN registers Longword access should be avoided 15 8 7 HCAN Medium Speed Mode In medium speed mode the HCAN registe...

Page 440: ...mitted retains its state To avoid this one of the following countermeasures must be executed Transmission must not be canceled by TXCR When transmission is normally completed after the CAN bus has recovered TXPR is cleared and the HCAN recovers the normal state To cancel transmission the corresponding bit to TXCR must be written to 1 continuously until the bit becomes 0 TXPR and TXCR are cleared a...

Page 441: ...ssors multi processor communication Figure 16 1 is a block diagram of the SSU 16 1 Features Choice of master mode and slave mode Choice of standard mode and bidirectional mode Synchronous serial communication with devices with different clock polarity and clock phase Choice of 8 16 32 bit width of transmit receive data Full duplex communication capability The shift register is incorporated enablin...

Page 442: ...ock selector Internal data bus Bus interface SSI Shiftout Shiftin OEI TXI TEI Legend SSCRH SSCRL SSMR SSER SSSR SSTDR0 to SSTDR3 SSRDR0 to SSRDR3 SSTRSR SS control register H SS control register L SS mode register SS enable register SS status register SS transmit data register SS receive data register SS transmit recive shift register SSRDR 0 SSRDR 1 SSRDR 2 SSRDR 3 SSTDR 0 SSTDR 1 SSTDR 2 SSTDR 3...

Page 443: ...r L SSCRL SS mode register SSMR SS enable register SSER SS status register SSSR SS transmit data register 0 to 3 SSTDR0 to SSTDR3 SS receive data register 0 to 3 SSRDR0 to SSRDR3 16 3 1 SS Control Register H SSCRH SSCRH specifies master slave device selection bidirectional mode enable SSO pin output value selection SSCK pin selection and SCS pin selection Bit Bit Name Initial Value R W Description...

Page 444: ...hat of the last bit can be modified by operating this bit before or after transmission When modifying the output level use the MOV instruction after clearing the SOLP bit to 0 Since writing to this bit during data transmission causes malfunctions this bit should not be modified 0 Serial data output is modified to low level 1 Serial data output is modified to high level 3 SOLP 0 R SOL Bit Write Pro...

Page 445: ...er 16 3 2 SS Control Register L SSCRL SSCRL selects software reset and transmit receive data width Bit Bit Name Initial Value R W Description 7 6 All 0 Reserved The write value should always be 0 5 SRES 0 R W Software Reset Setting this bit to 1 forcibly resets the SSU internal sequencer After that this bit is automatically cleared The ORER TEND TDRE RDRF and CE bits in SSSR and the TE and RE bits...

Page 446: ...y Selection Selects SSCK clock polarity 0 High output in idle mode and low output in active mode 1 Low output in idle mode and high output in active mode 5 CPHS 0 R W Clock Phase Selection Selects SSCK clock phase 0 Data changes at the first edge 1 Data is latched at the first edge 4 3 All 0 Reserved The write value should always be 0 2 1 0 CKS2 CKS1 CKS0 0 0 0 R W R W R W Transfer Clock Rate Sele...

Page 447: ... Enable When this bit is set to 1 reception is enabled 5 4 All 0 Reserved The write value should always be 0 3 TEIE 0 R W Transmit End Interrupt Enable When this bit is set to 1 TEI interrupt request is enabled 2 TIE 0 R W Transmit Interrupt Enable When this bit is set to 1 TXI interrupt request is enabled 1 RIE 0 R W Receive Interrupt Enable When this bit is set to 1 RXI interrupt request is enab...

Page 448: ...s and loses data received later While ORER 1 continuous serial reception cannot be continued Serial transmission cannot be continued either Setting condition When the next reception data is transferred to SSRDR while RDRF 1 Clearing condition When 0 is written to ORER after reading ORER 1 5 4 All 0 Reserved The write value should always be 0 3 TEND 1 R Transmit End Setting condition When the last ...

Page 449: ... Clearing conditions When 0 is written to the TDRE bit after reading TDRE 1 When data is written to SSTDR with TE 1 When data is transferred by the DTC 1 RDRF 0 R W Receive Data Register Full Indicates whether or not SSRDR contains received data Setting condition When receive data is transferred from SSTRSR to SSRDR after successful data reception Clearing conditions When 0 is written to RDRF afte...

Page 450: ...use it is determined that a master device has terminated the transfer Data reception does not continue while the CE bit is set to 1 Reset the SSU internal sequencer by setting the SRES bit in SSCRL to 1 before resuming transfer after incomplete error Setting condition When a low level is input to the SCS pin in master device mode MSS in SSCRH 1 When a 1 is input to the SCS pin during slave device ...

Page 451: ... length is selected SSRDR0 and SSRDR1 are valid When 32 bit data length is selected SSRDR0 to SSRDR3 are valid When the SSU has received 1 byte data it transfers the received serial data from SSTRSR to SSRDR where it is stored After this SSTRSR is receive enabled Since SSTRSR and SSRDR function as a double buffer in this way continuous receive operations can be performed Read SSRDR after confirmin...

Page 452: ...ase polarity and transfer data depends on the combination of CPOS and CPHS in SSMR Figure 16 2 shows the relationship Setting the MLS bit specifies that MSB or LSB first communication When MLS 0 data is transferred from the LSB to MSB When MLS 1 data is transferred from the MSB to LSB SSCK CPOS 0 1 When CPHS 0 2 When CPHS 1 SSCK CPOS 1 SSI SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSCK C...

Page 453: ...hen BIDE 0 standard mode MSS 0 TE 1 and RE 1 3 When BIDE 1 bidirectional mode MSS 1 and TE or RE 1 4 When BIDE 1 bidirectional mode MSS 0 and TE or RE 1 SSO SSI SSCK SSO SSI SSCK SSO SSI SSCK SSO SSI Figure 16 3 Relationship between Data I O Pins and the Shift Register 16 4 4 Data Transmission and Data Reception The SSU performs data communications using the bus with four lines the clock line SSCK...

Page 454: ...tputs a transfer clock and data In slave device mode when a low level signal is input to the SCS pin and a transfer clock is input to the SSCK pin the SSU outputs data in synchronization with the transfer clock Writing transmit data to SSTDR after the TE bit is set to 1 clears the TDRE bit to 0 and the SSTDR contents is transferred to SSTRSR After that the SSU sets the TDRE bit to 1 and starts tra...

Page 455: ... 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SSO TDRE TEND LSI operation User operation LSI operation User operation LSI operation User operation TXI interrupt generated TEI interrupt generated TEI interrupt generated TXI interrupt generated TEI interrupt generated TXI interrupt generated Data written to SSTDR0 Data written to...

Page 456: ...omatically cleared Data transferd from SSTDR to SSTRSR Set TDRE to 1 to start transmission Continuous data transmission Read TEND in SSSR TEND 1 Clear TEND to 0 Clear TE in SSER to 0 End transmission Figure 16 6 Example of Data Transmission Flowchart Data Reception Figure 16 7 shows an example of reception operation and figure 16 8 shows an example of data reception flowchart When receiving data t...

Page 457: ...th rising edge of the transfer clock the ORER bit in SSSR is set to 1 This indicates that an overrun error OEI has occurred At this time data reception is stopped While the ORER bit in SSSR is set to 1 reception is not performed To resume the reception clear the ORER bit to 0 ...

Page 458: ...Bit 7 LSI operation Dummy read SSRDR0 Dummy read SSRDR0 Dummy read SSRDR0 Read SSRDR0 User operation LSI operation User operation LSI operation User operation SSTDR0 LSB first transmission SSTDR0 MSB first transmission RXI interrupt generated RXI interrupt generated RXI interrupt generated RXI interrupt generated Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 B...

Page 459: ...Start Initialization RE 1 reception enabled Dummy read SSRDR Read SSRDR ORER 1 RDRF 1 Continous data reception Read received data in SSRDR RDRF automatically cleared RE 0 Read received data in SSRDR End reception Overrun error processing Clear ORER in SSSR End reception Note Hatching boxes represent SSU internal operations Figure 16 8 Example of Data Reception Flowchart Data Transmission Reception...

Page 460: ...t SSTDR is ready to be written to After that data can be written to SSTDR The TDRE bit is automatically cleared to 0 by writing data to SSTDR 3 5 4 Transmission reception started TE 1 RE 1 Read TDRE in SSSR TDRE 1 Yes Yes Yes No No No No Write transmit data to SSTDR TDRE automatically cleared Data transferred from SSTDR to SSTRSR TDRE set to 1 to start transmission Read SSSR ORER 1 RDRF 1 Read rec...

Page 461: ... Internal clocked Hi Z Figure 16 10 Arbitration Detection Timing Before Transfer φ MSS Transfer start CE Hi Z Transfer end Arbitration detection period Figure 16 11 Arbitration Detection Timing After Transfer End 16 5 Interrupt Requests The SSU interrupt requests consist of transmit data register empty transmit end receive data register full overrun error and conflict error Of these interrupt sour...

Page 462: ...i0 Transmit data register empty TXI TIE 1 TDRE 1 Transmit end TEI TEIE 1 TEND 1 1 SSERT_i1 Overrun error OEI RIE 1 ORER 1 Conflict error CEI CEIE 1 CE 1 Receive data register full RXI RIE 1 RDRF 1 Transmit data register empty TXI TIE 1 TDRE 1 Transmit end TEI TEIE 1 TEND 1 When interrupt conditions shown in table 16 2 are satisfied and the I bit in CCR is 0 the CPU executes interrupt exception pro...

Page 463: ...me 11 08 µs per channel at 24 MHz operation Two operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16 bit data register for each channel Sample and hold function Three conversion start methods Software 16 bit timer pulse unit TPU conversion start trigger External trigger signal Interr...

Page 464: ...D C S R A D C R A D D R D A D D R C A D D R B A D D R A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A Conversion start trigger from TPU φ 2 φ 4 φ 8 φ 16 AVCC Vref AVSS ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D Figure 17 1 Block Diagram of A D Conv...

Page 465: ... Analog section power supply and reference voltage Analog ground pin AVSS Input Analog section ground and reference voltage Reference voltage pin Vref Input Reference voltage of A D conversion Analog input pin 0 AN0 Input Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Group 0 analog input pins Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog ...

Page 466: ...to store conversion results for each channel are shown in table 17 2 The converted 10 bit data is stored in bits 6 to 15 in ADDR The lower 6 bits are always read as 0 The data bus between the CPU and the A D converter is 8 bits wide The upper byte can be read directly from the CPU however the lower byte should be read via a temporary register The temporary register contents are transferred from th...

Page 467: ...ed by an ADI interrupt and ADDR is read 6 ADIE 0 R W A D Interrupt Enable A D conversion end interrupt ADI is enabled when this bit is set to 1 5 ADST 0 R W A D Start Clearing this bit to 0 stops A D conversion and the A D converter enters the wait state Setting this bit to 1 starts A D conversion In single mode this bits is automatically cleared to 0 when conversion on the specified channel is co...

Page 468: ...o 3 Select analog input channels When SCAN 0 When SCAN 1 0000 AN0 0000 AN0 0001 AN1 0001 AN0 AN1 0010 AN2 0010 AN0 to AN2 0011 AN3 0011 AN0 to AN3 0100 AN4 0100 AN4 0101 AN5 0101 AN4 AN5 0110 AN6 0110 AN4 to AN6 0111 AN7 0111 AN4 to AN7 1000 AN8 1000 AN8 1001 AN9 1001 AN8 AN9 1010 AN10 1010 AN8 to AN10 1011 AN11 1011 AN8 to AN11 1100 AN12 1100 AN12 1101 AN13 1101 AN12 AN13 1110 AN14 1110 AN12 to A...

Page 469: ...tware 01 A D conversion is started by TPU conversion start trigger 10 Setting prohibited 11 A D conversion is started by the ADTRG pin 5 4 All 1 Reserved These bits are always read as 1 3 2 CKS1 CKS0 0 0 R W R W Clock Select 0 and 1 Specify the A D conversion time The conversion time should be changed only when ADST 0 Specify a value within the range shown in table 23 7 in section 23 Electrical Ch...

Page 470: ...is automatically cleared to 0 and the A D converter enters the wait state If the ADST bit is cleared to 0 during A D conversion the conversion is stopped and the A D converter enters the wait state 17 4 2 Scan Mode In scan mode A D conversion is to be performed sequentially on the specified channels up to four channels as follows 1 When the ADST bit is set to 1 by software TPU or external trigger ...

Page 471: ...g time tSPL The length of tD varies depending on the timing of the write access to ADCSR Therefore the total conversion time varies within the range shown in table 17 3 In scan mode the values given in table 17 3 indicate the first conversion time The second and subsequent conversion time is shown in table 17 4 In both cases set bits CKS1 and CKS0 in ADCR within the range shown in table 23 7 in se...

Page 472: ...yp Max Min Typ Max Min Typ Max A D conversion start delay tD 18 33 10 17 6 9 4 5 Input sampling time tSPL 127 63 31 15 A D conversion time tCONV 515 530 259 266 131 134 67 68 Note All values represent the number of states Table 17 4 A D Conversion Time Scan Mode CKS1 CKS0 Conversion Time State 0 512 Fixed 0 1 256 Fixed 0 128 Fixed 1 1 64 Fixed ...

Page 473: ...gger signal ADST A D conversion Figure 17 3 External Trigger Input Timing 17 5 Interrupt Source When A D conversion is completed the A D converter generates an A D conversion end interrupt ADI The ADI interrupt request is enabled when the ADIE bit is set to 1 while the ADF bit in ADCSR is set to 1 after A D conversion is completed The DTC can be activated by an ADI interrupt Having the converted d...

Page 474: ...age value B 0000000000 H 000 to B 0000000001 H 001 see figure 17 5 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from B 1111111110 H 3FE to B 1111111111 H 3FF see figure 17 5 Nonlinearity error The error with respect to the ideal A D conversion characteristic between zero voltage and full scale voltage ...

Page 475: ...tal output Ideal A D conversion characteristic Analog input voltage Figure 17 4 A D Conversion Accuracy Definitions FS Digital output Ideal A D conversion characteristic Nonlinearity error Analog input voltage Offset error Actual A D conversion characteristic Full scale error Figure 17 5 A D Conversion Accuracy Definitions ...

Page 476: ...D conversion in single mode with a large capacitance provided externally the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance is ignored However as a low pass filter effect is obtained in this case it may not be possible to follow an analog signal with a large differential coefficient e g 5 mV µs or greater see figure 17 6 When conver...

Page 477: ...ry due to inductance adversely affecting A D conversion values Also digital circuitry must be isolated from the analog input signals AN0 to AN15 and analog power supply AVcc by the analog ground AVss Also the analog ground AVss should be connected at one point to a stable digital ground Vss on the board 17 7 6 Notes on Noise Countermeasures A protection circuit should be connected in order to prev...

Page 478: ...Rin Input impedance Figure 17 7 Example of Analog Input Protection Circuit Table 17 6 Analog Pin Specifications Item Min Max Unit Analog input capacitance 20 pF Permissible signal source impedance 5 kΩ 20 pF AN0 to AN15 Note Values are reference values 10 k To A D converter Figure 17 8 Analog Input Pin Equivalent Circuit ...

Page 479: ...to both byte data and word data The on chip RAM can be enabled or disabled by means of the RAME bit in the system control register SYSCR For details on SYSCR refer to section 3 2 2 System Control Register SYSCR Product Model ROM Type Capacity Address H8S 2628 Series HD64F2628 Flash memory version 8 kbytes H FFD000 to H FFEFBF HD6432628 8 kbytes H FFD000 to H FFEFBF HD6432627 Masked ROM version 6 k...

Page 480: ...Rev 1 0 09 02 page 444 of 568 ...

Page 481: ...h memory can be reprogrammed up to 100 times Three programming modes Boot mode User mode Programmer mode On board programming erasing can be done in boot mode in which the boot program built into the chip is started to erase or program of the entire flash memory In normal user program mode individual blocks can be erased or programmed Programmer mode Flash memory can be programmed erased in progra...

Page 482: ...AMER Figure 19 1 Block Diagram of Flash Memory 19 2 Mode Transitions When the mode pins and the FWE pin are set in the reset state and a reset start is executed this LSI enters an operating mode as shown in figure 19 2 In user mode flash memory can be read but not programmed or erased The boot user program and programmer modes are provided as modes to write and erase the flash memory The differenc...

Page 483: ...on possible 2 This LSI transits to programmer mode by using the dedicated PROM programmer 0 MD2 0 MD1 1 FWE 1 0 0 MD1 1 MD2 1 FWE 0 MD1 1 MD2 1 FWE 1 Figure 19 2 Flash Memory State Transitions Table 19 1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program 2 1 2 3 1 Erase erase verify 2 Program program ve...

Page 484: ...nsfer When boot mode is entered the boot program in this LSI originally incorporated in the chip is started and the programming control program in the host is transferred to RAM via SCI communication The boot program required for flash memory erasing is automatically transferred to the RAM boot program area 3 Flash memory initialization The erase program in the boot program area in RAM is executed...

Page 485: ...rase control program should be prepared in the host or in the flash memory 2 Programming erase control program transfer When user program mode is entered user software confirms this fact executes transfer program in the flash memory and transfers the programming erase control program to RAM 3 Flash memory initialization The programming erase program in RAM is executed and the flash memory is initi...

Page 486: ... 00047F H 00087F H 000C7F H 00107F H 007FFF H 00807F H 00BFFF H 0007FF H 000BFF H 000FFF H 01FFFF H 00C07F H 00DFFF H 00E07F H 00FFFF H 01007F H 017FFF H 01807F H 000400 H 000401 H 000402 H 000780 H 000781 H 000782 H 000800 H 000801 H 000802 H 000B80 H 000B81 H 000B82 H 000F80 H 000F81 H 000F82 H 007F80 H 007F81 H 007F82 H 00BF80 H 00BF81 H 00BF82 H 00DF80 H 00DF81 H 00DF82 H 00FF80 H 00FF81 H 00F...

Page 487: ...dware MD2 Input Sets this LSI s operating mode MD1 Input Sets this LSI s operating mode MD0 Input Sets this LSI s operating mode TxD2 Output Serial transmit data output RxD2 Input Serial receive data input 19 5 Register Descriptions The flash memory has the following registers Flash memory control register 1 FLMCR1 Flash memory control register 2 FLMCR2 Erase block register 1 EBR1 Erase block regi...

Page 488: ...e erase setup state When it is cleared to 0 the erase setup state is cancelled 4 PSU1 0 R W Program Setup When this bit is set to 1 the flash memory changes to the program setup state When it is cleared to 0 the program setup state is cancelled Set this bit to 1 before setting the P1 bit in FLMCR1 3 EV1 0 R W Erase Verify When this bit is set to 1 the flash memory changes to erase verify mode When...

Page 489: ... set more than one bit at a time otherwise all the bits in EBR1 are automatically cleared to 0 Bit Bit Name Initial Value R W Description 7 EB7 0 R W When this bit is set to 1 8 kbytes of EB7 H 00E000 to H 00FFFF will be erased 6 EB6 0 R W When this bit is set to 1 8 kbytes of EB6 H 00C000 to H 00DFFF will be erased 5 EB5 0 R W When this bit is set to 1 16 kbytes of EB5 H 008000 to H 00BFFF will b...

Page 490: ...er RAMER RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real time flash memory programming RAMER settings should be made in user mode or user program mode To ensure correct operation of the emulation function the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified If accessed normal access exec...

Page 491: ...am mode At reset start in reset mode this LSI changes to a mode depending on the MD pin settings and FWE pin setting as shown in table 19 3 The input level of each pin must be defined four states before the reset ends When boot mode is entered the boot program built into this LSI is initiated The boot program transfers the programming control program from the externally connected host to on chip R...

Page 492: ...e host s transfer bit rate and system clock frequency of this LSI there will be a discrepancy between the bit rates of the host and the chip To operate the SCI properly set the host s transfer bit rate and system clock frequency of this LSI within the ranges listed in table 19 5 5 In boot mode a part of the on chip RAM area is used by the boot program The area H FFE800 to H FFEFBF is used to store...

Page 493: ...der byte Receives data H AA Transmits 1 byte of programming control program repeated for N times Receives data H AA Transfer of programming control program Flash memory erase Boot program initiation Echobacks the 2 byte data received Branches to programming control program transferred to on chip RAM and starts execution Echobacks received data to host and also transfers it to RAM repeated for N ti...

Page 494: ...sample procedure for programming erasing in user program mode Prepare a user program erase control program in accordance with the description in section 19 8 Flash Memory Programming Erasing Yes No Program erase Transfer user program erase control program to RAM Reset start Branch to user program erase control program in RAM Execute user program erase control program flash memory rewrite Branch to...

Page 495: ...programming 1 Set RAMER to overlap part of RAM onto the area for which real time programming is required 2 Emulation is performed using the overlapping RAM 3 After the program data has been confirmed the RAMS bit is cleared thus releasing the RAM overlap 4 The data written in the overlapping RAM is written into the flash memory space EB0 Start of emulation program Set RAMER Write tuning data to ov...

Page 496: ...ash memory blocks emulation protection In this state setting the P1 or E1 bit in FLMCR1 to 1 does not make a transition to program mode or erase mode 5 A RAM area cannot be erased by execution of software in accordance with the erase algorithm 6 Block area EB0 contains the vector table When performing RAM emulation the vector table is needed in the overlap RAM H 000000 Flash memory EB0 Flash memor...

Page 497: ...ed addresses 2 Programming should be performed in units of 128 bytes A 128 byte data must be transferred even if data to be written is fewer than 128 bytes In this case H FF data must be written to the extra addresses 3 Prepare the following data storage areas in RAM A 128 byte programming data area a 128 byte reprogramming data area and a 128 byte additional programming data area Perform reprogra...

Page 498: ...essively write 128 byte data from additional programming data area in RAM to flash memory Reprogram Data Computation Table Reprogram Data X Verify Data V Additional Programming Data Y 1 1 1 1 0 1 0 0 0 0 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed 0 1 1 1 0 1 0 1 0 0...

Page 499: ...words from the address to which a dummy write was performed 6 If the read data is not erased successfully set erase mode again and repeat the erase erase verify sequence as before Note that the number of repetitions of the erase erase verify sequence should be less than 100 19 8 3 Interrupt Handling when Programming Erasing Flash Memory All interrupts including the NMI interrupt should be disabled...

Page 500: ...t address as verify address H FF dummy write to verify address SWE bit 1 n 1 ESU1 bit 1 E1 bit 1 Wait 1 µs Wait 100 µs E1 bit 0 EV1 bit 1 Wait 10 µs ESU1 bit 0 Wait 10 µs Wait 10 µs Wait 20 µs EV1 bit 0 n n 1 Wait 4 µs SWE bit 0 Wait 100 µs EV1 bit 0 n 100 Wait 4 µs SWE bit 0 Wait 100 µs Erase failure End of erasing Wait 2 µs No No Yes Yes No No Yes Yes Figure 19 10 Erase Erase Verify Flowchart ...

Page 501: ...ister 1 EBR1 erase protection can be set for individual blocks When EBR1 is set to H 00 erase protection is set for all blocks 19 9 3 Error Protection In error protection an error is detected when CPU runaway occurs during flash memory programming erasing or operation is not performed in accordance with the program erase algorithm and the program erase operation is aborted Aborting the program era...

Page 502: ...read and written to Standby mode All flash memory circuits are halted Table 19 6 shows the correspondence between the operating modes of the H8S 2628 Series and the flash memory When the flash memory returns to its normal operating state from standby mode a period to settle the power supply circuits that were stopped is needed When the flash memory returns to its normal operating state bits STS2 t...

Page 503: ...L XTAL SCK2 to SCK0 SCKCR STC1 STC0 LPWRCR Legend LPWRCR Low power control register SCKCR System clock control register Clock oscillator PLL circuit 1 2 4 Clock selection circuit System clock to φ pin Internal clock to peripheral modules Bus master clock to CPU and DTC Medium speed clock divider Bus master clock selection circuit φ 2 to φ 32 f Figure 20 1 Block Diagram of Clock Pulse Generator The...

Page 504: ...TOP 0 R W φ Clock Output Disable Controls φ output High speed Mode Medium Speed Mode 0 φ output 1 Fixed high Sleep Mode 0 φ output 1 Fixed high Software Standby Mode 0 Fixed high 1 Fixed high Hardware Standby Mode 0 High impedance 1 High impedance 6 to 4 All 0 Reserved These bits are always read as 0 3 STCS 0 R W Frequency Multiplication Factor Switching Mode Select Selects the operation when the ...

Page 505: ...m speed clock is φ 16 101 Medium speed clock is φ 32 11X Setting prohibited Legend X Don t care 20 1 2 Low Power Control Register LPWRCR Bit Bit Name Initial Value R W Description 7 to 4 All 0 Reserved The write value should always be 0 3 2 All 0 R W Reserved These bits can be read from and write to but should not be set to 1 1 0 STC1 STC0 0 0 R W R W Frequency Multiplication Factor The STC bits s...

Page 506: ...AT cut parallel resonance crystal should be used EXTAL XTAL Rd CL2 CL1 CL1 CL2 10 to 22 pF Figure 20 2 Connection of Crystal Resonator Example Table 20 1 Damping Resistance Value Frequency MHz 4 8 12 16 20 24 Rd Ω 500 200 0 0 0 0 Figure 20 3 shows the equivalent circuit of the crystal resonator Use a crystal resonator that has the characteristics shown in table 20 2 XTAL CL AT cut parallel resonan...

Page 507: ... the XTAL pin is left open ensure that stray capacitance does not exceed 10 pF When complementary clock is input to the XTAL pin the external clock input should be fixed high in standby mode EXTAL XTAL EXTAL XTAL External clock input Open External clock input a XTAL pin left open b Complementary clock input at XTAL pin Figure 20 4 External Clock Input Examples ...

Page 508: ...t Conditions VCC 5 0 V 10 Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 20 8 ns Figure 20 5 External clock input high pulse width tEXH 20 8 ns External clock rise time tEXr 5 ns External clock fall time tEXf 5 ns tEXH tEXL tEXr tEXf VCC 0 5 EXTAL Figure 20 5 External Clock Input Timing ...

Page 509: ...are standby mode 4 The clock pulse generator stops and the value set in STC0 and STC1 becomes valid 5 Software standby mode is cleared and a transition time is secured in accordance with the setting in STS0 to STS2 6 After the set transition time has elapsed this LSI resumes operation using the target multiplication factor If a PC break is set for the SLEEP instruction software standby mode is ent...

Page 510: ...cillator pin 20 6 2 Note on Board Design When designing the board place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins Other signal lines should be routed away from the oscillator circuit as shown in figure 20 6 This is to prevent induction from interfering with correct oscillation CL2 Avoid Signal A Signal B CL1 This LSI XTAL EXTAL Figure 20 6 Note o...

Page 511: ...9 02 page 475 of 568 PLLCAP PLLVSS VCC VCL VSS Values are preliminary recommended values Note CB is laminated ceramic R1 3 k C1 470 pF CB 0 1 F CB 0 1 F Figure 20 7 External Circuitry Recommended for PLL Circuit ...

Page 512: ...Rev 1 0 09 02 page 476 of 568 ...

Page 513: ...um speed mode 3 Sleep mode 4 Module stop mode 5 Software standby mode 6 Hardware standby mode 2 to 6 are power down modes Sleep mode is a CPU state medium speed mode is a CPU and bus master state and module stop mode is an internal peripheral function including bus masters other than the CPU state Some of these states can be combined After a reset the LSI is in high speed mode Figure 21 1 shows po...

Page 514: ...an interrupt the transition cannot be made on interrupt source generation alone Ensure that interrupt handling is performed after accepting the interrupt request From any state except hardware standby mode a transition to the reset state occurs when is driven low From any state a transition to hardware standby mode occurs when is driven low Figure 21 1 Mode Transition Diagram Table 21 1 Low Power ...

Page 515: ... Operate Operate Operate Operate Retained High impedance TPU PPG Operate Operate Operate Halted retained Halted retained Halted reset WDT Operate Operate Operate Operate Halted retained Halted reset SCI HCAN A D Operate Operate Operate Halted reset Halted reset Halted reset RAM Operate Medium speed operation Operate DTC Operate Retained Retained Peripheral functions SSU Operate Operate Operate Hal...

Page 516: ...ter C MSTPCRC 21 1 1 Standby Control Register SBYCR SBYCR is an 8 bit readable writable register that performs software standby mode control Bit Bit Name Initial Value R W Description 7 SSBY 0 R W Software Standby This bit specifies the transition mode after executing the SLEEP instruction 0 Shifts to sleep mode when the SLEEP instruction is executed 1 Shifts to software standby mode when the SLEE...

Page 517: ...ect a wait time of 8ms oscillation settling time or more depending on the operating frequency With an external clock select a wait time of 2 ms or more 000 Standby time 8192 states 001 Standby time 16384 states 010 Standby time 32768 states 011 Standby time 65536 states 100 Standby time 131072 states 101 Standby time 262144 states 110 Reserved 111 Standby time 16 states 3 1 R W Reserved The write ...

Page 518: ...me Initial Value R W Module 7 MSTPA7 0 R W 6 MSTPA6 0 R W Data transfer controller DTC 5 MSTPA5 1 R W 16 bit timer pulse unit TPU 4 MSTPA4 1 R W 8 bit timer TMR_0 TMR_1 3 MSTPA3 1 R W Programmable pulse generator PPG 2 MSTPA2 1 R W 1 MSTPA1 1 R W A D converter 0 MSTPA0 1 R W 8 bit timer TMR_2 TMR_3 MSTPCRB Bit Bit Name Initial Value R W Module 7 MSTPB7 1 R W Serial communication interface 0 SCI0 6...

Page 519: ...than bus masters always operate on the high speed clock φ In medium speed mode a bus access is executed in the specified number of states with respect to the bus master operating clock For example if φ 4 is selected as the operating clock on chip memory is accessed in 4 states and internal I O registers in 8 states Medium speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0 A transition...

Page 520: ...ters are retained Other peripheral modules do not stop 21 3 2 Clearing Sleep Mode Sleep mode is cleared by any interrupt or signals at the RES or STBY pins Exiting Sleep Mode by Interrupts When an interrupt occurs sleep mode is exited and interrupt exception processing starts Sleep mode is not exited if the interrupt is disabled or if interrupts other than NMI are masked by the CPU Exiting Sleep M...

Page 521: ...errupt request signal is input clock oscillation starts and after the time set in bits STS0 to STS2 in SBYCR has elapsed stable clocks are supplied to the entire chip software standby mode is cleared and interrupt exception handling is started When clearing software standby mode with an IRQ0 to IRQ5 interrupt set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority...

Page 522: ...ng Set bits STS0 to STS2 so that the standby time is at least 2 ms the oscillation settling time Table 21 3 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 24 MHz 20 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz Unit 0 8192 states 0 34 0 41 0 51 0 68 0 8 1 0 1 3 2 0 0 1 16384 states 0 68 0 82 1 0 1 3 1 6 2 0 2 7 4 1 0 32768 states 1 4 1 6 2 0 2 7 3 3 4 1 5 5 8 2 0 1 1 65536 states...

Page 523: ...EG bit in SYSCR cleared to 0 falling edge specification then the NMIEG bit is set to 1 rising edge specification the SSBY bit is set to 1 and a SLEEP instruction is executed causing a transition to software standby mode Software standby mode is then cleared at the rising edge on the NMI pin Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG 1 SSBY 1 Oscillation stabilization time tOSC2 Softw...

Page 524: ... pin When the STBY pin is driven high while the RES pin is low the reset state is set and clock oscillation is started Ensure that the RES pin is held low until the clock oscillator settles at least 8 ms the oscillation settling time when using a crystal oscillator When the RES pin is subsequently driven high a transition is made to the program execution state via the reset exception handling stat...

Page 525: ...o 1 module operation stops at the end of the bus cycle and a transition is made to module stop mode The CPU continues operating independently When the corresponding MSTP bit is cleared to 0 module stop mode is cleared and the module starts operating at the end of the bus cycle In module stop mode the internal states of modules other than the SCI HCAN and A D converter are retained After reset clea...

Page 526: ... high Fixed high High impedance 21 8 Usage Notes 21 8 1 I O Port Status In software standby mode I O port states are retained Therefore there is no reduction in current consumption for the output current when a high level signal is output 21 8 2 Current Consumption during Oscillation Stabilization Wait Period Current consumption increases during the oscillation settling wait period 21 8 3 DTC Modu...

Page 527: ...Rev 1 0 09 02 page 491 of 568 21 8 5 Writing to MSTPCR MSTPCR should only be written to by the CPU ...

Page 528: ...Rev 1 0 09 02 page 492 of 568 ...

Page 529: ... The access size is indicated 2 Register bits Bit configurations of the registers are described in the same order as the register addresses Reserved bits are indicated by in the bit name column Bit number in the bit name column indicates that the whole register is allocated as a counter or for holding data When registers consist of 16 bits bits are described from the MSB side 3 Register states in ...

Page 530: ...80C HCAN 16 4 Receive complete register RXPR 16 H F80E HCAN 16 4 Remote request register RFPR 16 H F810 HCAN 16 4 Interrupt register IRR 16 H F812 HCAN 16 4 Mailbox interrupt mask register MBIMR 16 H F814 HCAN 16 4 Interrupt mask register IMR 16 H F816 HCAN 16 4 Receive error counter REC 8 H F818 HCAN 16 4 Transmit error counter TEC 8 H F819 HCAN 16 4 Unread message status register UMSR 16 H F81A ...

Page 531: ...essage control 2 7 MC2 7 8 H F836 HCAN 16 4 Message control 2 8 MC2 8 8 H F837 HCAN 16 4 Message control 3 1 MC3 1 8 H F838 HCAN 16 4 Message control 3 2 MC3 2 8 H F839 HCAN 16 4 Message control 3 3 MC3 3 8 H F83A HCAN 16 4 Message control 3 4 MC3 4 8 H F83B HCAN 16 4 Message control 3 5 MC3 5 8 H F83C HCAN 16 4 Message control 3 6 MC3 6 8 H F83D HCAN 16 4 Message control 3 7 MC3 7 8 H F83E HCAN 1...

Page 532: ...essage control 6 8 MC6 8 8 H F857 HCAN 16 4 Message control 7 1 MC7 1 8 H F858 HCAN 16 4 Message control 7 2 MC7 2 8 H F859 HCAN 16 4 Message control 7 3 MC7 3 8 H F85A HCAN 16 4 Message control 7 4 MC7 4 8 H F85B HCAN 16 4 Message control 7 5 MC7 5 8 H F85C HCAN 16 4 Message control 7 6 MC7 6 8 H F85D HCAN 16 4 Message control 7 7 MC7 7 8 H F85E HCAN 16 4 Message control 7 8 MC7 8 8 H F85F HCAN 1...

Page 533: ...ol 11 1 MC11 1 8 H F878 HCAN 16 4 Message control 11 2 MC11 2 8 H F879 HCAN 16 4 Message control 11 3 MC11 3 8 H F87A HCAN 16 4 Message control 11 4 MC11 4 8 H F87B HCAN 16 4 Message control 11 5 MC11 5 8 H F87C HCAN 16 4 Message control 11 6 MC11 6 8 H F87D HCAN 16 4 Message control 11 7 MC11 7 8 H F87E HCAN 16 4 Message control 11 8 MC11 8 8 H F87F HCAN 16 4 Message control 12 1 MC12 1 8 H F880 ...

Page 534: ...C15 1 8 H F898 HCAN 16 4 Message control 15 2 MC15 2 8 H F899 HCAN 16 4 Message control 15 3 MC15 3 8 H F89A HCAN 16 4 Message control 15 4 MC15 4 8 H F89B HCAN 16 4 Message control 15 5 MC15 5 8 H F89C HCAN 16 4 Message control 15 6 MC15 6 8 H F89D HCAN 16 4 Message control 15 7 MC15 7 8 H F89E HCAN 16 4 Message control 15 8 MC15 8 8 H F89F HCAN 16 4 Message data 0 1 MD0 1 8 H F8B0 HCAN 16 4 Mess...

Page 535: ...HCAN 16 4 Message data 3 3 MD3 3 8 H F8CA HCAN 16 4 Message data 3 4 MD3 4 8 H F8CB HCAN 16 4 Message data 3 5 MD3 5 8 H F8CC HCAN 16 4 Message data 3 6 MD3 6 8 H F8CD HCAN 16 4 Message data 3 7 MD3 7 8 H F8CE HCAN 16 4 Message data 3 8 MD3 8 8 H F8CF HCAN 16 4 Message data 4 1 MD4 1 8 H F8D0 HCAN 16 4 Message data 4 2 MD4 2 8 H F8D1 HCAN 16 4 Message data 4 3 MD4 3 8 H F8D2 HCAN 16 4 Message data...

Page 536: ...HCAN 16 4 Message data 7 4 MD7 4 8 H F8EB HCAN 16 4 Message data 7 5 MD7 5 8 H F8EC HCAN 16 4 Message data 7 6 MD7 6 8 H F8ED HCAN 16 4 Message data 7 7 MD7 7 8 H F8EE HCAN 16 4 Message data 7 8 MD7 8 8 H F8EF HCAN 16 4 Message data 8 1 MD8 1 8 H F8F0 HCAN 16 4 Message data 8 2 MD8 2 8 H F8F1 HCAN 16 4 Message data 8 3 MD8 3 8 H F8F2 HCAN 16 4 Message data 8 4 MD8 4 8 H F8F3 HCAN 16 4 Message data...

Page 537: ...4 Message data 11 5 MD11 5 8 H F90C HCAN 16 4 Message data 11 6 MD11 6 8 H F90D HCAN 16 4 Message data 11 7 MD11 7 8 H F90E HCAN 16 4 Message data 11 8 MD11 8 8 H F90F HCAN 16 4 Message data 12 1 MD12 1 8 H F910 HCAN 16 4 Message data 12 2 MD12 2 8 H F911 HCAN 16 4 Message data 12 3 MD12 3 8 H F912 HCAN 16 4 Message data 12 4 MD12 4 8 H F913 HCAN 16 4 Message data 12 5 MD12 5 8 H F914 HCAN 16 4 Me...

Page 538: ...AN 16 4 Message data 15 8 MD15 8 8 H F92F HCAN 16 4 HCAN monitor register HCANMON 8 H FA00 HCAN 16 4 SS control register H_0 SSCRH_0 8 H FB00 SSU_0 16 3 SS control register L_0 SSCRL_0 8 H FB01 SSU_0 16 3 SS mode register_0 SSMR_0 8 H FB02 SSU_0 16 3 SS enable register_0 SSER_0 8 H FB03 SSU_0 16 3 SS status register_0 SSSR_0 8 H FB04 SSU_0 16 3 SS transmit data register 0_0 SSTDR0_0 8 H FB06 SSU_0...

Page 539: ...2 TCSR_2 8 H FDC2 TMR_2 8 2 Timer control status register_3 TCSR_3 8 H FDC3 TMR_3 8 2 Timer constant register A_2 TCORA_2 8 H FDC4 TMR_2 8 2 Timer constant register A_3 TCORA_3 8 H FDC5 TMR_3 8 2 Timer constant register B_2 TCORB_2 8 H FDC6 TMR_2 8 2 Timer constant register B_3 TCORB_3 8 H FDC7 TMR_3 8 2 Timer counter_2 TCNT_2 8 H FDC8 TMR_2 8 2 Timer counter_3 TCNT_3 8 H FDC9 TMR_3 8 2 Standby co...

Page 540: ...egister L NDERL 8 H FE29 PPG 8 2 Output data register H PODRH 8 H FE2A PPG 8 2 Output data register L PODRL 8 H FE2B PPG 8 2 Next data register H NDRH 8 H FE2C PPG 8 2 Next data register L NDRL 8 H FE2D PPG 8 2 Next data register H NDRH 8 H FE2E PPG 8 2 Next data register L NDRL 8 H FE2F PPG 8 2 Port 1 data direction register P1DDR 8 H FE30 PORT 8 2 Port 3 data direction register P3DDR 8 H FE32 PO...

Page 541: ...L_3 TGRAL_3 8 H FE89 TPU_3 16 2 Timer general register BH_3 TGRBH_3 8 H FE8A TPU_3 16 2 Timer general register BL_3 TGRBL_3 8 H FE8B TPU_3 16 2 Timer general register CH_3 TGRCH_3 8 H FE8C TPU_3 16 2 Timer general register CL_3 TGRCL_3 8 H FE8D TPU_3 16 2 Timer general register DH_3 TGRDH_3 8 H FE8E TPU_3 16 2 Timer general register DL_3 TGRDL_3 8 H FE8F TPU_3 16 2 Timer control register_4 TCR_4 8...

Page 542: ...t priority register B IPRB 8 H FEC1 INT 8 2 Interrupt priority register C IPRC 8 H FEC2 INT 8 2 Interrupt priority register D IPRD 8 H FEC3 INT 8 2 Interrupt priority register E IPRE 8 H FEC4 INT 8 2 Interrupt priority register F IPRF 8 H FEC5 INT 8 2 Interrupt priority register G IPRG 8 H FEC6 INT 8 2 Interrupt priority register H IPRH 8 H FEC7 INT 8 2 Interrupt priority register J IPRJ 8 H FEC9 ...

Page 543: ...ister DH_0 TGRDH_0 8 H FF1E TPU_0 16 2 Timer general register DL_0 TGRDL_0 8 H FF1F TPU_0 16 2 Timer control register_1 TCR_1 8 H FF20 TPU_1 16 2 Timer mode register_1 TMDR_1 8 H FF21 TPU_1 16 2 Timer I O control register_1 TIOR_1 8 H FF22 TPU_1 16 2 Timer interrupt enable register_1 TIER_1 8 H FF24 TPU_1 16 2 Timer status register_1 TSR_1 8 H FF25 TPU_1 16 2 Timer counter H_1 TCNTH_1 8 H FF26 TPU...

Page 544: ...FF70 TMR_0 8 2 Timer counter_1 TCNT_1 8 H FF71 TMR_1 8 2 Timer control status register_0 TCSR_0 8 H FF74 WDT_0 16 2 Timer counter_0 TCNT_0 8 H FF75 WDT_0 16 2 Reset control status register RSTCSR 8 H FF77 WDT 16 2 Serial mode register_0 SMR_0 8 H FF78 SCI_0 8 2 Bit rate register_0 BRR_0 8 H FF79 SCI_0 8 2 Serial control register_0 SCR_0 8 H FF7A SCI_0 8 2 Transmit data register_0 TDR_0 8 H FF7B SC...

Page 545: ...DCR 8 H FF99 A D 8 2 Flash memory control register 1 FLMCR1 8 H FFA8 ROM 8 2 Flash memory control register 2 FLMCR2 8 H FFA9 ROM 8 2 Erase block register 1 EBR1 8 H FFAA ROM 8 2 Erase block register 2 EBR2 8 H FFAB ROM 8 2 Port 1 register PORT1 8 H FFB0 PORT 8 2 Port 3 register PORT3 8 H FFB2 PORT 8 2 Port 4 register PORT4 8 H FFB3 PORT 8 2 Port 7 register PORT7 8 H FFB6 PORT 8 2 Port 9 register P...

Page 546: ...CR10 TXCR9 TXCR8 TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 RXPR RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 RFPR RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 R...

Page 547: ...25 ID 24 ID 23 ID 22 ID 21 MC0 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC0 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC1 1 DLC3 DLC2 DLC1 DLC0 MC1 2 MC1 3 MC1 4 MC1 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC1 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC1 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC1 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC2 1 DLC3 DLC2 DLC1 DLC0 MC2 2 MC2...

Page 548: ...ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC4 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC5 1 DLC3 DLC2 DLC1 DLC0 MC5 2 MC5 3 MC5 4 MC5 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC5 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC5 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC5 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC6 1 DLC3 DLC2 DLC1 DLC0 MC6 2 MC6 3 MC6 4 MC6 5 ID 20 ID 19 ID 18 RTR I...

Page 549: ...13 ID 12 ID 11 ID 10 ID 9 ID 8 MC9 1 DLC3 DLC2 DLC1 DLC0 MC9 2 MC9 3 MC9 4 MC9 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC9 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC9 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC9 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC10 1 DLC3 DLC2 DLC1 DLC0 MC10 2 MC10 3 MC10 4 MC10 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC10 6 ID 28 ID 27 ID 26 ID 25 ID 24...

Page 550: ...ID 8 MC13 1 DLC3 DLC2 DLC1 DLC0 MC13 2 MC13 3 MC13 4 MC13 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC13 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 MC13 7 ID 7 ID 6 ID 5 ID 4 ID 3 ID 2 ID 1 ID 0 MC13 8 ID 15 ID 14 ID 13 ID 12 ID 11 ID 10 ID 9 ID 8 MC14 1 DLC3 DLC2 DLC1 DLC0 MC14 2 MC14 3 MC14 4 MC14 5 ID 20 ID 19 ID 18 RTR IDE ID 17 ID 16 MC14 6 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21...

Page 551: ...2 Bit 1 Bit 0 MD1 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD1 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD1 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD1 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD2 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD2 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD2 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD2 4 Bi...

Page 552: ...Bit 2 Bit 1 Bit 0 MD5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD5 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD5 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD6 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD6 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD6 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD6 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD6 ...

Page 553: ...t 1 Bit 0 MD9 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD9 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD10 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD10 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD10 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD10 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD10 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD10 6 ...

Page 554: ... Bit 0 MD13 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD13 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD14 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD14 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD14 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD14 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD14 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MD14 6 B...

Page 555: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR3 _0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR0 _0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR1 _0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR2 _0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR3 _0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSCRH _1 MSS BIDE SOL SOLP SCKS CSSI CSSO SSU_1 SSCRL _1 SRES DATSI DATSO ...

Page 556: ...MIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_3 TCSR_2 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TCSR_3 CMFB CMFA OVF OS3 OS2 OS1 OS0 TCORA _2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORA _3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORB _2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORB _3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNT_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B...

Page 557: ...A5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTC DTCERB DTCEB7 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCERC DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCERD DTCED7 DTCED6 DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCERE DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCERF DTCEF7 DTCEF6 DTCEF5 DTCEF4 DTCEF3 DTCEF2 DTCEF1 DTCEF0 DTCERG DTCEG7 DTCEG6 DTCEG5 DTCEG4 DTCEG3 D...

Page 558: ...DR P32ODR P31ODR P30ODR PAODR PA3ODR PA2ODR PA1ODR PA0ODR PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR TCR_3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_3 TMDR_3 BFB BFA MD3 MD2 MD1 MD0 TIORH_3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_3 TTGE TCIEV TGIED TGIEC T...

Page 559: ...5 TMDR_5 MD3 MD2 MD1 MD0 TIOR_5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_5 TTGE TCIEU TCIEV TGIEB TGIEA TSR_5 TCFD TCFU TCFV TGFB TGFA TCNTH_5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TCNTL_5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRAH_5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TGRAL_5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRBH_5 Bit 15 Bit 14 Bit...

Page 560: ...D3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 TCFV TGFD TGFC TGFB TGFA TCNTH_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TCNTL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRAH_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TGRAL_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRBH_0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit...

Page 561: ...it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRBH_2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TGRBL_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_0 TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_1 TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TCSR_1 CMFB CMFA OVF OS3 OS2 OS1 OS0 TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 562: ...it 0 SSR_2 1 TDRE RDRF ORER FER PER TEND MPB MPBT SSR_2 2 TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SCMR_2 SDIR SINV SMIF ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A D ADDRAL AD1 AD0 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRBL AD1 AD0 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRCL AD1 AD0 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRDL AD1 AD0 ADCSR ADF...

Page 563: ...2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Notes 1 For buffer operation 2 For free operation 3 Normal serial communication interface mode 4 Smart Card interface mode Some bit functions of SMR differ in normal serial communication interface mode and Smart Card interface mode ...

Page 564: ...zed IMR Initialized Initialized Initialized Initialized REC Initialized Initialized Initialized Initialized TEC Initialized Initialized Initialized Initialized UMSR Initialized Initialized Initialized Initialized LAFML Initialized Initialized Initialized Initialized LAFMH Initialized Initialized Initialized Initialized MC0 1 Initialized Initialized Initialized Initialized MC0 2 Initialized Initial...

Page 565: ...ed Initialized Initialized Initialized MC3 4 Initialized Initialized Initialized Initialized MC3 5 Initialized Initialized Initialized Initialized MC3 6 Initialized Initialized Initialized Initialized MC3 7 Initialized Initialized Initialized Initialized MC3 8 Initialized Initialized Initialized Initialized MC4 1 Initialized Initialized Initialized Initialized MC4 2 Initialized Initialized Initial...

Page 566: ...ed Initialized Initialized Initialized MC7 5 Initialized Initialized Initialized Initialized MC7 6 Initialized Initialized Initialized Initialized MC7 7 Initialized Initialized Initialized Initialized MC7 8 Initialized Initialized Initialized Initialized MC8 1 Initialized Initialized Initialized Initialized MC8 2 Initialized Initialized Initialized Initialized MC8 3 Initialized Initialized Initial...

Page 567: ...Initialized Initialized Initialized MC11 6 Initialized Initialized Initialized Initialized MC11 7 Initialized Initialized Initialized Initialized MC11 8 Initialized Initialized Initialized Initialized MC12 1 Initialized Initialized Initialized Initialized MC12 2 Initialized Initialized Initialized Initialized MC12 3 Initialized Initialized Initialized Initialized MC12 4 Initialized Initialized Ini...

Page 568: ...tialized Initialized Initialized Initialized MC15 7 Initialized Initialized Initialized Initialized MC15 8 Initialized Initialized Initialized Initialized MD0 1 Initialized Initialized Initialized Initialized MD0 2 Initialized Initialized Initialized Initialized MD0 3 Initialized Initialized Initialized Initialized MD0 4 Initialized Initialized Initialized Initialized MD0 5 Initialized Initialized...

Page 569: ...ed Initialized Initialized Initialized MD3 8 Initialized Initialized Initialized Initialized MD4 1 Initialized Initialized Initialized Initialized MD4 2 Initialized Initialized Initialized Initialized MD4 3 Initialized Initialized Initialized Initialized MD4 4 Initialized Initialized Initialized Initialized MD4 5 Initialized Initialized Initialized Initialized MD4 6 Initialized Initialized Initial...

Page 570: ...d Initialized Initialized Initialized MD8 1 Initialized Initialized Initialized Initialized MD8 2 Initialized Initialized Initialized Initialized MD8 3 Initialized Initialized Initialized Initialized MD8 4 Initialized Initialized Initialized Initialized MD8 5 Initialized Initialized Initialized Initialized MD8 6 Initialized Initialized Initialized Initialized MD8 7 Initialized Initialized Initiali...

Page 571: ... Initialized Initialized Initialized MD12 2 Initialized Initialized Initialized Initialized MD12 3 Initialized Initialized Initialized Initialized MD12 4 Initialized Initialized Initialized Initialized MD12 5 Initialized Initialized Initialized Initialized MD12 6 Initialized Initialized Initialized Initialized MD12 7 Initialized Initialized Initialized Initialized MD12 8 Initialized Initialized In...

Page 572: ...ialized Initialized SSU_0 SSCRL_0 Initialized Initialized Initialized Initialized SSMR_0 Initialized Initialized Initialized Initialized SSER_0 Initialized Initialized Initialized Initialized SSSR_0 Initialized Initialized Initialized Initialized SSTDR0_0 Initialized Initialized Initialized Initialized SSTDR1_0 Initialized Initialized Initialized Initialized SSTDR2_0 Initialized Initialized Initia...

Page 573: ...ORT TCR_2 Initialized Initialized TMR_2 TCR_3 Initialized Initialized TMR_3 TCSR_2 Initialized Initialized TCSR_3 Initialized Initialized TCORA_2 Initialized Initialized TCORA_3 Initialized Initialized TCORB_2 Initialized Initialized TCORB_3 Initialized Initialized TCNT_2 Initialized Initialized TCNT_3 Initialized Initialized SBYCR Initialized SYSTEM SYSCR Initialized SCKCR Initialized MDCR Initia...

Page 574: ...Initialized PCR Initialized Initialized PPG PMR Initialized Initialized NDERH Initialized Initialized NDERL Initialized Initialized PODRH Initialized Initialized PODRL Initialized Initialized NDRH Initialized Initialized NDRL Initialized Initialized NDRH Initialized Initialized NDRL Initialized Initialized P1DDR Initialized PORT P3DDR Initialized P7DDR Initialized PADDR Initialized PBDDR Initializ...

Page 575: ...Initialized Initialized TGRBL_3 Initialized Initialized TGRCH_3 Initialized Initialized TGRCL_3 Initialized Initialized TGRDH_3 Initialized Initialized TGRDL_3 Initialized Initialized TCR_4 Initialized Initialized TPU_4 TMDR_4 Initialized Initialized TIOR_4 Initialized Initialized TIER_4 Initialized Initialized TSR_4 Initialized Initialized TCNTH_4 Initialized Initialized TCNTL_4 Initialized Initi...

Page 576: ...zed INT IPRB Initialized Initialized IPRC Initialized Initialized IPRD Initialized Initialized IPRE Initialized Initialized IPRF Initialized Initialized IPRG Initialized Initialized IPRH Initialized Initialized IPRJ Initialized Initialized IPRK Initialized Initialized IPRM Initialized Initialized RAMER Initialized Initialized ROM P1DR Initialized PORT P3DR Initialized P7DR Initialized PADR Initial...

Page 577: ...CR_1 Initialized Initialized TPU_1 TMDR_1 Initialized Initialized TIOR_1 Initialized Initialized TIER_1 Initialized Initialized TSR_1 Initialized Initialized TCNTH_1 Initialized Initialized TCNTL_1 Initialized Initialized TGRAH_1 Initialized Initialized TGRAL_1 Initialized Initialized TGRBH_1 Initialized Initialized TGRBL_1 Initialized Initialized TCR_2 Initialized Initialized TPU_2 TMDR_2 Initial...

Page 578: ...ized TDR_0 Initialized Initialized Initialized Initialized SSR_0 Initialized Initialized Initialized Initialized RDR_0 Initialized Initialized Initialized Initialized SCMR_0 Initialized Initialized Initialized Initialized SMR_2 Initialized Initialized Initialized Initialized SCI_2 BRR_2 Initialized Initialized Initialized Initialized SCR_2 Initialized Initialized Initialized Initialized TDR_2 Init...

Page 579: ...tialized ADCSR Initialized Initialized Initialized Initialized ADCR Initialized Initialized Initialized Initialized FLMCR1 Initialized Initialized ROM FLMCR2 Initialized Initialized EBR1 Initialized Initialized EBR2 Initialized Initialized PORT1 Initialized PORT PORT3 Initialized PORT4 Initialized PORT7 Initialized PORT9 Initialized PORTA Initialized PORTB Initialized PORTC Initialized PORTD Initi...

Page 580: ...Rev 1 0 09 02 page 544 of 568 ...

Page 581: ...TAL EXTAL Vin 0 3 to VCC 0 3 V Input voltage port 4 and 9 Vin 0 3 to AVCC 0 3 V Input voltage except XTAL EXTAL port 4 and 9 Vin 0 3 to VCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 C Storage temperature Tstg 55 to 125 C Caution Permanent damage to th...

Page 582: ... 0 7 V voltage VT VT VCC 0 05 V Input high voltage RES STBY NMI MD2 to MD0 FWE VIH VCC 0 9 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Ports 1 3 7 A to D F HRxD VCC 0 7 VCC 0 3 V Ports 4 and 9 AVCC 0 7 AVCC 0 3 V Input low voltage RES STBY NMI MD2 to MD0 FWE VIL 0 3 VCC 0 1 V EXTAL 0 3 VCC 0 2 V Ports 1 3 7 A to D F HRxD 0 3 VCC 0 2 V Ports 4 9 0 3 AVCC 0 2 V Output high All output pins VOH VCC 0 5 V IOH 20...

Page 583: ...f 24 MHz VCC 5 0 V reference values Standby TBD TBD µA Ta 50 C mode TBD µA 50 C Ta Analog power supply During A D conversion AlCC 2 5 4 0 mA AVCC 5 0 V current Idle 5 0 µA RAM standby voltage VRAM 2 0 V Notes 1 If the A D converter is not used do not leave the AVCC and AVSS pins open Apply a voltage between 4 5 V and 5 5 V to the AVCC pin by connecting them to VCC for instance 2 Current consumptio...

Page 584: ...Total of all output pins VCC 4 5 to 5 5 V IOL 100 mA Permissible output high current per pin All output pins VCC 4 5 to 5 5 V IOH 2 0 mA Permissible output high current total Total of all output pins VCC 4 5 to 5 5 V IOH 30 mA Note To protect chip reliability do not exceed the output current values in table 23 3 23 3 AC Characteristics Figure 23 1 shows the test conditions for the AC characteristi...

Page 585: ...tem Symbol Min Max Unit Test Conditions Clock cycle time tcyc 41 6 250 ns Figure 23 2 Clock high pulse width tCH TBD ns Clock low pulse width tCL TBD ns Clock rise time tCr TBD ns Clock fall time tCf TBD ns Oscillation settling time at reset crystal tOSC1 20 ms Figure 23 3 Oscillation settling time in software standby crystal tOSC2 8 ms Figure 21 3 External clock output settling delay time tDEXT 2...

Page 586: ...V VSS AVSS 0 V φ 4MHz to 24MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns Figure 23 4 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns Figure 23 5 NMI hold time tNMIH 10 ns NMI pulse width exiting software standby mode tNMIW 200 ns IRQ setup time tIRQS 150 ns IRQ hold time tIRQH 10 n...

Page 587: ...Rev 1 0 09 02 page 551 of 568 tRESW tRESS φ tRESS Figure 23 4 Reset Input Timing φ tIRQS Edge input tIRQH tNMIS tNMIH tIRQS Level input NMI i 0 to 5 tNMIW tIRQW Figure 23 5 Interrupt Input Timing ...

Page 588: ... setup time tPRS 25 Input data hold time tPRH 25 Realtime input port data hold time tRTIPH 4 tcyc Figure 23 7 TPU Timer output delay time tTOCD 40 ns Figure 23 8 Timer input setup time tTICS 25 Timer clock input setup time tTCKS 25 ns Figure 23 9 Timer clock Single edge tTCKWH 1 5 tcyc pulse width Both edges tTCKWL 2 5 SCI Input clock Asynchro nous tScyc 4 tcyc Figure 23 10 cycle Synchro nous 6 In...

Page 589: ... 23 14 Note The HCAN input signal is asynchronous However its state is judged to have changed at the rising edge two clock cycles of the φ clock signal shown in figure 23 12 The HCAN output signal is also asynchronous Its state changes based on the rising edge two clock cycles of the φ clock signal shown in figure 23 12 Table 23 7 Timing of SSU Conditions VCC 4 5 V to 5 5 V AVCC 4 5 V to 5 5 V VSS...

Page 590: ...ock rise time Master Slave tRISE 15 TBD ns Clock fall time Master Slave tFALL 25 TBD ns Data input setup time Master Slave tSU 30 TBD ns Data input hold time Master Slave tH 10 TBD ns SCS setup time Master Slave tLEAD 1 TBD tCYC SCS hold time Master Slave tLAG 1 TBD tCYC Data output delay time Master Slave tOD 40 TBD ns Data output hold time Master Slave tOH 0 TBD ns Continuous transfer delay time...

Page 591: ... 3 7 A to D F write Figure 23 6 I O Port Input Output Timing tRTIPH φ Port D input Figure 23 7 Realtime Input Port Data Input Timing φ tTICS tTOCD Output compare output Input capture input Note TIOCA0 to TIOCA5 TIOCB0 to TIOCB5 TIOCC0 TIOCC3 TIOCD0 TIOCD3 Figure 23 8 TPU Input Output Timing ...

Page 592: ...k Input Timing tScyc tSCKr tSCKW SCK0 to SCK2 tSCKf Figure 23 10 SCK Clock Input Timing SCK0 to SCK2 TxD0 to TxD2 transmit data RxD0 to RxD2 receive data tTXD tRXH tRXS Figure 23 11 SCI Input Output Timing Clocked Synchronous Mode φ tTRGS Figure 23 12 A D Converter External Trigger Input Timing ...

Page 593: ...eive data tHTXD tHRXS tHRXH Figure 23 13 HCAN Input Output Timing φ PO15 to 8 tPOD Figure 23 14 PPG Output Timing tLEAD tSUCYC tFALL tRISE tLAG tHI tH tOH tLO tOD tSU output SSCK output CPOS 1 SCS output CPOS 0 SSO output SSI input Figure 23 15 SSU Timing Master CPHS 1 ...

Page 594: ...OD tSU SCS output SSCK output CPOS 1 SCS output CPOS 0 SSO output SSI input Figure 23 16 SSU Timing Master CPHS 0 tLEAD tSUCYC tFALL tRISE tLAG tHI tH tLO tTD tREL tOD tOH tSU tSA input SSCK input CPOS 1 SCS input CPOS 0 SSO input SSI output tLO tHI Figure 23 17 SSU Timing Slave CPHS 1 ...

Page 595: ...Rev 1 0 09 02 page 559 of 568 tLEAD tSA tSUCYC tFALL tRISE tLAG tHI tTD tH tREL tOH tLO tLO tHI tOD tSU input SSCK input CPOS 1 SCS input CPOS 0 SSO input SSI output Figure 23 18 SSU Timing Slave CPHS 0 ...

Page 596: ...VCC 4 5 V to 5 5 V VSS AVSS 0V φ 4MHz to 24MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 10 200 µs Analog input capacitance 20 pF Permissible signal source impedance 5 kΩ Nonlinearity error 3 5 LSB Offset error 3 5 LSB Full scale error 3 5 LSB Quantization 0 5 LSB Absolute accuracy 4 0 LSB ...

Page 597: ...ime wait tsp10 8 10 12 µs Additional programming time wait Wait time after P1 bit clear 1 tcp 5 5 µs Wait time after PSU1 bit clear 1 tcpsu 5 5 µs Wait time after PV1 bit setting 1 tspv 4 4 µs Wait time after H FF dummy write 1 tspvr 2 2 µs Wait time after PV1 bit clear 1 tcpv 2 2 µs Wait time after SWE bit clear 1 tcswe 100 100 µs Maximum programming count 1 4 N 1000 Times Erase Wait time after S...

Page 598: ...programming algorithm set the max value 1000 for the maximum programming count n The wait time after P1 bit setting should be changed as follows according to the value of the programming counter n Programming counter n 1 to 6 tsp30 30 µs Programming counter n 7 to 1000 tsp200 200 µs In additional programming Programming counter n 1 to 6 tsp10 10 µs 5 For the maximum erase time tE max the following...

Page 599: ... port Port 4 7 T T T Input port Port 7 7 T T Keep I O port Port 9 7 T T T Input port Port A 7 T T Keep I O port Port B 7 T T Keep I O port Port C 7 T T Keep I O port Port D 7 T T Keep I O port PF7 7 T T DDR 0 T DDR 1 H DDR 0 T DDR 1 Clock output PF6 PF5 PF4 PF3 PF2 PF1 PF0 7 T T Keep I O port HTxD 7 H T H Output HRxD 7 Input T T Input Legend H High level T High impedance Keep Input port becomes hi...

Page 600: ...6432627 C Package Dimensions The package dimension that is shown in the Hitachi Semiconductor Package Data Book has priority Hitachi Code JEDEC JEITA Mass reference value FP 100M Conforms 1 2 g Dimension including the plating thickness Base material dimension 0 10 16 0 0 2 1 0 0 5 0 1 16 0 0 2 3 05 Max 75 51 50 26 1 25 76 100 14 0 8 0 5 0 08 M 0 22 0 05 2 70 0 17 0 05 0 12 0 13 0 12 1 0 0 20 0 04 ...

Page 601: ...ister Indirect with Displacement 38 Register Indirect with Post Increment39 Register Indirect with Pre Decrement39 Bcc 25 34 Bit Rate 386 break address 85 88 break conditions 88 Bus Arbitration 95 bus cycle 93 Bus Masters 95 Clock Pulse Generator 467 Condition Field 37 Condition Code Register CCR 20 CPU Operating Modes 12 Advanced Mode 13 Normal Mode 12 data direction register 121 data register 12...

Page 602: ...tructions 32 Block Data Transfer Instructions 36 Branch Instructions 34 Data Transfer Instructions 27 Logic Operations Instructions 30 Shift Instructions 31 System Control Instructions 35 Interrupt Control Modes 76 Interrupt Controller 63 Interrupt Exception Handling Vector Table 72 Interrupt Mask Bit 20 interrupt mask level 19 interrupt priority register IPR 63 Interrupts ADI 437 CMIA 257 CMIB 25...

Page 603: ...40 IRR 370 494 510 528 ISCR 68 503 521 537 ISR 70 504 521 537 LAFMH 378 494 511 528 LAFML 378 494 511 528 LPWRCR 469 503 521 537 MBCR 363 494 510 528 MBIMR 374 494 510 528 MC 380 494 511 528 MCR 358 494 510 528 MD 382 498 515 532 MDCR 48 503 520 537 MRA 100 MRB 101 MSTPCR 482 503 520 537 NDER 266 504 521 538 NDR 268 504 521 538 P1DDR 125 504 522 538 P1DR 126 506 524 540 PADDR 138 504 522 538 PADR ...

Page 604: ...SR 247 503 520 537 TDR 294 508 526 542 TEC 376 494 510 528 TGR 205 505 522 539 TIER 190 505 522 539 TIOR 173 505 522 539 TMDR 171 505 522 539 TSR 294 505 522 539 TSTR 195 506 523 540 TSYR 196 506 523 540 TXACK 366 494 510 528 TXCR 365 494 510 528 TXPR 364 494 510 528 UMSR 377 494 510 528 Registres TCNTH 524 Reset 55 Serial Communication Interface 291 Asynchronous Mode 315 bit rate 308 Break 353 fr...

Page 605: ...t Edition September 2002 Published by Business Operation Division Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2002 All rights reserved Printed in Japan ...

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