Hitachi H8S/2627, Hardware Manual

Page: 131 / 605

Rev. 1.0, 09/02, page 95 of 568
7.1.4 On-chip SSU Module and Realtime Input Port Data Register Access Timing
The on-chip SSU module or realtime input port data register is accessed in three states. At this
time, a data bus width is 16 bits. Figure 7.4 shows the SSU module access timing.
T1 T3 T2
φ
Internal address bus
Bus cycle
Address
Read data
Write data
SSU read signal
Internal data bus
SSU write signal
Internal data bus
Read
Write
Figure.7.4 On-chip SSU Module Access Cycle
7.2 Bus Arbitration
The Bus Controller has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
control the bus.
7.2.1 Order of Priority of the Bus Masters
Each bus master requests the bus mastership by means of a bus request signal. The bus arbiter
detects the bus masters’ bus request signals, and if the bus mastership is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is cancelled.
The order of priority of the bus mastership is as follows:
(High) DTC > CPU (Low)