Hitachi H8S/2627, Hardware Manual

Page: 202 / 605

Rev. 1.0, 09/02, page 166 of 568
10.3.1 Timer Control Register (TCR)
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The TPU has a total of six TCR registers, one for each channel (channel 0 to 5). TCR
register settings should be conducted only when TCNT operation is stopped.
Bit Bit Name Initial value R/W Description
7
6
5 CCLR2
CCLR1
CCLR0 0
0
0 R/W
R/W
R/W Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 10.3 and 10.4 for details.
4
3 CKEG1
CKEG0 0
0 R/W
R/W Clock Edge 0 and 1
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g.
φ
/4 both edges =
φ
/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and the
phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
φ
/4 or slower. This setting is ignored if the input clock
is
φ
/1, or when overflow/underflow of another channel
is selected.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
Legend X: Don’t care
2
1
0 TPSC2
TPSC1
TPSC0 0
0
0 R/W
R/W
R/W Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables10.5 to10.10 for details.