Hitachi H8S/2627, Hardware Manual

Page: 129 / 605

Rev. 1.0, 09/02, page 93 of 568
Section 7 Bus Controller
The H8S/2600 CPU is driven by a system clock, denoted by the symbol
φ
.
The bus controller controls a memory cycle and a bus cycle. Different methods are used to access
on-chip memory and on-chip support modules. The bus controller also has a bus arbitration
function, and controls the operation of the internal bus masters: the CPU and data transfer
controller (DTC).
7.1 Basic Timing
The period from one rising edge of
φ
to the next is referred to as a "state." The memory cycle or
bus cycle consists of one, two, three, or four states. Different methods are used to access on-chip
memory and on-chip support modules.
7.1.1 On-Chip Memory Access Timing (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 7.1 shows the on-chip memory access cycle.
T1
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
Write
Figure 7.1 On-Chip Memory Access Cycle