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10.2 Input/Output
Pins .............................................................................................................. 163
10.3 Register
Descriptions ........................................................................................................ 164
10.3.1 Timer Control Register (TCR)............................................................................. 166
10.3.2 Timer Mode Register (TMDR) ............................................................................ 171
10.3.3 Timer I/O Control Register (TIOR) ..................................................................... 173
10.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 190
10.3.5 Timer Status Register (TSR)................................................................................ 192
10.3.6 Timer Counter (TCNT)........................................................................................ 195
10.3.7 Timer General Register (TGR) ............................................................................ 195
10.3.8 Timer Start Register (TSTR) ............................................................................... 195
10.3.9 Timer Synchro Register (TSYR) ......................................................................... 196
10.4 Operation .......................................................................................................................... 196
10.4.1 Basic
Functions.................................................................................................... 196
10.4.2 Synchronous
Operation........................................................................................ 203
10.4.3 Buffer
Operation .................................................................................................. 204
10.4.4 Cascaded
Operation ............................................................................................. 208
10.4.5 PWM
Modes ........................................................................................................ 209
10.4.6 Phase Counting Mode .......................................................................................... 214
10.5 Interrupt
Sources............................................................................................................... 221
10.6 DTC
Activation................................................................................................................. 223
10.7 A/D Converter Activation ................................................................................................. 223
10.8 Operation
Timing.............................................................................................................. 224
10.8.1 Input/Output
Timing ............................................................................................ 224
10.8.2 Interrupt Signal Timing........................................................................................ 228
10.9 Usage
Notes ...................................................................................................................... 231
10.9.1 Module Stop Mode Setting .................................................................................. 231
10.9.2 Input Clock Restrictions ...................................................................................... 231
10.9.3 Caution on Period Setting .................................................................................... 231
10.9.4 Conflict between TCNT Write and Clear Operations.......................................... 232
10.9.5 Conflict between TCNT Write and Increment Operations .................................. 233
10.9.6 Conflict between TGR Write and Compare Match.............................................. 234
10.9.7 Conflict between Buffer Register Write and Compare Match ............................. 235
10.9.8 Conflict between TGR Read and Input Capture .................................................. 236
10.9.9 Conflict between TGR Write and Input Capture ................................................. 237
10.9.10 Conflict between Buffer Register Write and Input Capture................................. 238
10.9.11 Conflict between Overflow/Underflow and Counter Clearing ............................ 239
10.9.12 Conflict between TCNT Write and Overflow/Underflow ................................... 240
10.9.13 Multiplexing of I/O Pins ...................................................................................... 240
10.9.14 Interrupts in Module Stop Mode.......................................................................... 240
Section 11 8-Bit Timers..................................................................................... 241
11.1 Features ............................................................................................................................. 241
11.2 Input/Output
Pins .............................................................................................................. 242
Summary of Contents for H8S/2627
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