77
CHAPTER 4 I/O PORTS
Table 4.1-2 Registers of Ports
Register name
Read/Write
Address
Initial value
Port 0 data register
(PDR0)
R/W
0000
H
XXXXXXXX
B
Port 0 data direction register
(DDR0)
W
*1
0001
H
00000000
B
Port 0 pull-up setting register
(PUL0)
R/W
0070
H
00000000
B
Port 3 data register
(PDR3)
R/W
000C
H
XXXXXXXX
B
Port 3 data direction register
(DDR3)
W
*1
000D
H
00000000
B
Port 3 pull-up setting register
(PUL3)
R/W
0071
H
00000000
B
Port 4 data register
(PDR4)
R/W
000F
H
----XXXX
B
Port 4 data direction register
(DDR4)
R/W
0010
H
----0000
B
Port 4 output form setting register
(OUT4)
R/W
0011
H
----0000
B
Port 5 data register
(PDR5)
R/W
0012
H
-------X
B
Port 5 data direction register
(DDR5)
R/W
0013
H
-------0
B
Port 5 pull-up setting register
(PUL5)
R/W
0072
H
-------0
B
Port 6 data register
(PDR6)
R/W
0060
H
------XX
B
Port 6 data direction register
*2
(DDR6)
R/W
0061
H
------00
B
Port 6 pull-up setting register
(PUL6)
R/W
0062
H
------00
B
Port 7 data register
(PDR7)
R/W
0063
H
-----XXX
B
Port 7 data direction register
(DDR7)
R/W
0064
H
-----000
B
Port 7 pull-up setting register
(PUL7)
R/W
0065
H
-----000
B
R/W : Readable and Writable
W
: Write only
X
: Undefined
*1
: DDR0 and DDR3 cannot be used for bit manipulation instructions.
*2
: DDR6 is not used in MB89F202/F202RA.
Summary of Contents for F2MC-8L F202RA
Page 2: ......
Page 4: ......
Page 32: ...16 CHAPTER 1 OVERVIEW ...
Page 90: ...74 CHAPTER 3 CPU ...
Page 142: ...126 CHAPTER 5 TIME BASE TIMER POPW A RETI ENDS END ...
Page 150: ...134 CHAPTER 6 WATCHDOG TIMER ...
Page 176: ...160 CHAPTER 7 8 BIT PWM TIMER ...
Page 220: ...204 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER ...
Page 240: ...224 CHAPTER 9 12 BIT PPG TIMER ...
Page 274: ...258 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL ...
Page 362: ...346 CHAPTER 15 BUZZER OUTPUT ...
Page 390: ...374 CHAPTER 17 FLASH MEMORY ...
Page 419: ...403 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 434: ...418 INDEX ...
Page 436: ......