Fujitsu F2MC-8L F202RA, Hardware Manual

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97
CHAPTER 4 I/O PORTS
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Port 5 pull-up setting register (PUL5)
When the ON setting of the pull-up resistor is selected by using the pull-up setting register, the pin state
will be "H" level (pull-up state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up
is invalid and the pin remains at Hi-Z.
Figure 4.5-2 Pull-up Setting Register (PUL5)
Table 4.5-3 Functions of Port 5 Registers
Register
name
Data
When being
read
When being
written
Read/Write Address Initial value
Port 5 data
register
(PDR5)
0
Pin state is "L"
level.
Output latch of "0" is
set and "L" level is
output to the pin in
output port mode.
R/W 00012
H
-------X
B
1
Pin state is "H"
level.
Output latch of "1" is
set and the pin in
output port mode is
set at Hi-Z.
Port 5 data
direction
register
(DDR5)
0 Input port pin
The pin is set to
function as an input
pin with output
transistor operation
disabled.
R/W 0013
H
-------0
B
1 Output port pin
The pin is set to
function as an output
pin with output
transistor operation
enabled.
R/W : Readable/Writable
X
: Undefined
PUL50
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0072
H
PUL50
-------0
B
R/W
R/W : Readable/Writable
: Unused
: Initial value
Address
Initial value
P50 pull-up OFF
P50 pull-up ON