Fujitsu F2MC-8L F202RA, Hardware Manual

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218
CHAPTER 9 12-BIT PPG TIMER
9.4.4 12-bit PPG Control Register 4 (RCR24)
The 12-bit PPG control register 4 comprises bits for setting a cycle period of 12-bit PPG
waveform outputs.
■
12-bit PPG Control Register 4 (RCR24)
Figure 9.4-5 12-bit PPG Control Register 4 (RCR24)
SCL11 to SCL6
XXXXXX
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0017
H
SCL11 SCL10 SCL9 SCL8 SCL7 SCL6 --000000
B
R/W R/W R/W R/W R/W R/W
R/W:
Readable/Writable
Address
Initial value
Cycle period setting bits
Compare value for the cycle period of 12-bit PPG outputs
: Unused
Table 9.4-4 Explanation of Functions of Each Bit in 12-bit PPG Control Register 4 (RCR24)
Bit name Function
bit7,
bit6
Unused bits
• Bit value is undefined when being read.
• Written value does not affect other operations.
bit5
to
bit0
SCL11 to SCL6:
Cycle period
setting bits
These bits are used to set the number of counts corresponding to the cycle period of
12-bit PPG waveform outputs (the compare value for cycle period), and the contents
of these bits and the SCL0 to SCL5 bits of RCR23 are compared with a count by the
counter.
Note:
Set a value that falls within the range of "000000000010
B
" to "111111111111
B
"
(002
H
to FFF
H
).