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342

CHAPTER 15 BUZZER OUTPUT

15.3

Pin of the Buzzer Output

The pin related to the buzzer output is P37/BZ/PPG.

■

P37/BZ/PPG Pin

The P37/BZ/PPG pin works as a general-purpose I/O (P37) pin, output pin for the buzzer output (BZ), or

output pin for the 12-bit PPG (PPG).

●

BZ pin

The BZ pin outputs the square wave for the buzzer of the frequency having been specified for the BZ pin.

When a buzzer output frequency is specified (other than BZCR:BZ2,BZ1,BZ0=000

), the P37/BZ/PPG pin

automatically works as the BZ pin regardless of the value of output latch. Even if the PPG output has been

enabled, it works as the BZ pin that has higher priority.

■

Block Diagram of the Pin Related to the Buzzer Output

Figure 15.3-1 Block Diagram of Pin Related to Buzzer Output

Note:

If pull-up resistor supported is specified by the pull-up setting register, the state of the pin in stop mode

(SPL=1) is not Hi-Z but "H" level (pull-up state). During a reset, however, the pull-up is disabled and

the state is Hi-Z.

DDR

Pch

Nch

PDR

PUL

7/BZ/PPG

(

PL=1)

Inter

l d

PDR re

top mode (

PL=1)

ll-

p re

tor

Peripher

l o

Peripher

PDR re

(At re

d-modify-write)

t l

tch

PDR write

DDR write

PUL re

PUL write

top mode

Summary of Contents for F2MC-8L F202RA

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MC 8L 8 BIT MICROCONTROLLER MB89202 F202RA Series HARDWARE MANUAL CM25 10153 2E ...

Page 2: ......

Page 3: ... the following support page URL http www fujitsu com global services microelectronics product micom support index html Check Sheet lists the minimal requirement items to be checked to prevent problems beforehand in system development Be sure to refer to the Check Sheet for the latest cautions on development ...

Page 4: ......

Page 5: ... This Manual This manual consists of the following 17 chapters and appendix CHAPTER 1 OVERVIEW This chapter describes the features and basic specification of the MB89202 F202RA series CHAPTER 2 HANDLING DEVICES This chapter describes the precautions to be taken when handling the MB89202 F202RA series CHAPTER 3 CPU This chapter describes the functions and operation of the CPU CHAPTER 4 I O PORTS Th...

Page 6: ... A D converter CHAPTER 13 UART This chapter describes the functions and operation of UART CHAPTER 14 8 BIT SERIAL I O This chapter describes the functions and operation of the 8 bit serial I O CHAPTER 15 BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output CHAPTER 16 WILD REGISTER FUNCTIONS This chapter describes the functions and operation of the wild registers CH...

Page 7: ...bed in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and cou...

Page 8: ...ulti use pins For multi use pins the names corresponding to functions are listed and divided by By writing 1 into the sleep bit of the standby control register STBC SLP Register name Bit name Register abbreviation Bit abbreviation Prohibit the output of interrupt request of the time base timer TBTC TBIE 0 Setting data Bit abbreviation Register abbreviation If interrupt enabled CCR I 1 is specified...

Page 9: ... Bank Pointer RP 31 3 3 General Purpose Registers 32 3 4 Interrupts 34 3 4 1 Interrupt Level Setting Registers ILR1 to ILR4 36 3 4 2 Steps in the Interrupt Operation 37 3 4 3 Multiple Interrupts 39 3 4 4 Interrupt Processing Time 40 3 4 5 Stack Operation at Interrupt Processing 41 3 4 6 Stack Area for Interrupt Processing 42 3 5 Reset 43 3 5 1 Reset Flag Register RSFR 45 3 5 2 External Reset Pin 4...

Page 10: ... Registers of Port 6 PDR6 DDR6 PUL6 103 4 6 2 Operations of Port 6 Functions 105 4 7 Port 7 107 4 7 1 Registers of Port 7 PDR7 DDR7 PUL7 109 4 7 2 Operations of Port 7 Functions 111 4 8 Programming Example of I O Port 113 CHAPTER 5 TIME BASE TIMER 115 5 1 Overview of Time base Timer 116 5 2 Configuration of Time base Timer 118 5 3 Time base Timer Control Register TBTC 119 5 4 Interrupt of Time bas...

Page 11: ...er TCR1 175 8 4 4 Timer Output Control Register TCR2 177 8 4 5 Timer 0 Data Register TDR0 178 8 4 6 Timer 1 Data Register TDR1 180 8 4 7 Capture Data Registers H and L TCPH and TCPL 182 8 5 8 16 bit Capture Timer Counter of Interrupts 183 8 6 Explanation of Operations of Interval Timer Functions 185 8 7 Operation of Counter Functions 189 8 8 Functions of Operations of Capture Functions 193 8 9 8 1...

Page 12: ...Register EIF2 252 11 5 Interrupt of External Interrupt Circuit 2 253 11 6 Operations of External Interrupt Circuit 2 254 11 7 Program Example for External Interrupt Circuit 2 256 CHAPTER 12 A D CONVERTER 259 12 1 Overview of A D Converter 260 12 2 Configuration of A D Converter 261 12 3 Pins of A D Converter 263 12 4 Registers of A D Converter 265 12 4 1 A D Control Register 1 ADC1 266 12 4 2 A D ...

Page 13: ... 327 14 8 8 Bit Serial I O Operation in Each Mode 329 14 9 Notes on Using 8 Bit Serial I O 333 14 10 Example of 8 Bit Serial I O Connection 334 14 11 Program Example for 8 Bit Serial I O 336 CHAPTER 15 BUZZER OUTPUT 339 15 1 Overview of the Buzzer Output 340 15 2 Configuration of the Buzzer Output 341 15 3 Pin of the Buzzer Output 342 15 4 Buzzer Register BZCR 343 15 5 Program Example for Buzzer O...

Page 14: ...of Writing to Erasing Flash Memory 367 17 5 1 Setting The Read Reset State 368 17 5 2 Writing Data 369 17 5 3 Erasing All Data Erasing Chips 371 17 6 Flash Security Feature 372 17 7 Notes on using Flash Memory 373 APPENDIX 375 APPENDIX A I O Map 376 APPENDIX B Overview of the Instructions 380 B 1 Addressing 383 B 2 Special Instructions 387 B 3 Bit Manipulation Instructions SETB and CLRB 391 B 4 F2...

Page 15: ... 24 3 1 1 Specific purpose Areas The summary is changed General purpose Register Area address 0100H to 01FFH is changed Vector Table Area Address FFC0H to FFFFH is changed 44 3 5 Reset Power on reset is changed Note is deleted 56 3 6 3 System Clock Control Register SYCC Figure 3 6 5 is changed 57 Table 3 6 1 is changed 130 6 3 Watchdog Control Register WDTC Figure 6 3 1 is changed 186 8 6 Explanat...

Page 16: ...rations Operating Mode 2 Only is changed Note is changed 358 17 1 Overview of Flash Memory High voltage supply on RST pin applicable to MB89F202RA only is added 370 17 5 2 Writing Data Figure 17 5 1 is changed F555 F554 394 B 4 F2 MC 8L Instructions List Table B 4 2 is changed No 22 DECW A is changed Page Changes For details refer to main body ...

Page 17: ...ion of the MB89202 F202RA series 1 1 Features of MB89202 F202RA Series 1 2 MB89202 F202RA Series Product Lineup 1 3 Differences between Models 1 4 Block Diagram of MB89202 F202RA Series 1 5 Pin Assignment 1 6 Package Dimensions 1 7 Pin Functions Description 1 8 I O Circuit Types ...

Page 18: ...mers 8 16 bit capture timer counter 8 bit capture timer counter 8 bit timer or 16 bit capture timer counter 8 bit PWM timer also available as an interval timer 21 bit time base timer Watchdog timer 10 bit A D converter 10 bit A D 8 channels Activation by 8 16 bit capture timer counter output is possible Programmable pulse generator PPG Pulse width and cycle are software selectable 12 bit PPG UART ...

Page 19: ...mode The CPU is stopped so that the current consumption is reduced by one third of normal consumption Up to 26 pins of I O ports General purpose I O ports CMOS 26 pins 4 of which can be used as N ch open drain I O ports Wild registers 2 byte data at two addresses are available When a specific address or data is used on a wild register the data in the ROM area is changed 16 KB Flash with read prote...

Page 20: ...sification Evaluation product for development Flash memory product read protection Mask ROM product ROM size 32K 8 bits External EPROM 2 16K 8 bits Internal Flash 16K 8 bits Internal mask ROM RAM size 512 8 bits Low power consumption standby mode Sleep mode and stop mode Process CMOS Operating voltage 1 2 7V to 5 5V 3 5V to 5 5V 2 2V to 5 5V 1 The minimum operating voltage varies with conditions s...

Page 21: ... 16384 tINST and 256 times 8 16 bit capture timer counter output 8 16 bit capture timer counter 8 bit capture timer counter 1 channel 8 bit timer or 16 bit capture timer counter 1 channel When timer 0 or a 16 bit counter is operating event counting operation by external clock input and square wave output are supported UART Transfer data length 6 7 or 8 bits 8 bitserial I O 8 bits length LSB first ...

Page 22: ...of a model with a flash is greater than that of a model with a mask ROM though the current consumption in sleep or stop mode is the same Notes For details on each package see Section 1 6 Package Dimensions For details on current consumption and electrical characteristics of A D converter see the electrical characteristics in the Data Sheet Table 1 3 1 Differences between Models Package MB89201 MB8...

Page 23: ...External interrupt2 wake up CMOS I O port Reset circuit Clock controller Main clock oscillator Port 4 Port 0 VCC VSS C 12 bit PPG Buzzer output CMOS I O port External interrupt1 8 16 bit capture timer counter 8 bit serial I O 8 bit PWM CMOS I O port Time base timer UART Internal bus Port 5 Port 3 Serial function switching UART prescaler P37 BZ PPG P35 INT11 P36 INT12 P34 TO INT10 P33 EC P32 UI SI ...

Page 24: ...f DIP 32P M06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC P03 INT23 AN7 P02 INT22 AN6 P01 INT21 AN5 P00 INT20 AN4 P43 AN3 P42 AN2 P41 AN1 P40 AN0 P72 P71 P70 P50 PWM P30 UCK SCK P31 UO SO P32 UI SI 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P04 INT24 P05 INT25 P06 INT26 P07 INT27 P60 P61 RST X0 X1 VSS P37 BZ PPG P36 INT12 P35 INT11 P34 TO INT10 P33 EC C Large current drive type ...

Page 25: ... 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 P04 INT24 P05 INT25 P06 INT26 P07 INT27 P60 P61 RST X0 X1 VSS P37 BZ PPG P36 INT12 P35 INT11 P34 TO INT10 N C P33 EC P32 UI SI P31 UO SO P30 UCK SCK P50 PWM N C C P70 P71 P72 P40 AN0 P41 AN1 P42 AN2 P43 AN3 P00 INT20 AN4 P01 INT21 AN5 P02 INT22 AN6 P03 INT23 AN7 VCC Large current drive type ...

Page 26: ...ch 1 778 mm Low space 10 16 mm Sealing method Plastic mold 32 pin plastic SH DIP DIP 32P M06 DIP 32P M06 C 2003 FUJITSU LIMITED D32018S c 1 1 350 010 8 89 0 25 1 778 070 1 27 050 10 16 400 INDEX 28 00 1 102 0 20 0 30 012 008 4 70 185 0 70 0 20 008 028 3 30 130 0 20 0 30 012 008 MAX 1 02 040 0 20 008 012 0 30 MIN 0 51 020 0 15 M 0 25 010 019 0 48 0 08 003 005 0 12 0 27 011 003 0 07 001 0 03 Dimensi...

Page 27: ...4P M03 C 2003 FUJITSU LIMITED F34003S c 2 3 11 00 0 10 433 004 6 10 0 10 8 10 0 20 240 004 319 008 A 009 003 003 0 07 0 08 0 24 INDEX 0 10 004 M 0 10 004 0 10 004 1 2 007 001 0 17 0 03 0 25 010 0 10 0 10 004 004 Stand off Details of A part Mounting height 1 25 0 20 0 10 004 008 049 0 8 0 50 0 20 020 008 0 60 0 15 024 006 1 17 34 18 0 65 0265 Dimensions in mm inches Note The values in parentheses a...

Page 28: ...put of the L signal 28 29 30 31 P00 INT20 AN4 P01 INT21 AN5 G General purpose CMOS I O ports These pins also serve as an input wake up input of external interrupt 2 or as an 10 bit A D converter analog input The input of external interrupt 2 is a hysteresis input 30 31 32 33 P02 INT22 AN6 P03 INT23 AN7 G General purpose CMOS I O ports These pins also serve as an input wake up input of external int...

Page 29: ...nput pin for external interrupt 1 The resource is a hysteresis input 11 11 P37 BZ PPG E General purpose CMOS I O ports This pin also serves as the buzzer output pin or the 12 bit PPG output pin 20 21 P50 PWM E General purpose CMOS I O ports This pin also serves as the 8 bit PWM timer output pin 24 to 27 26 to 29 P40 AN0 to P43 AN3 F General purpose CMOS I O ports These pins can also be used as N c...

Page 30: ... 2 Types Circuit Remarks A At an oscillation feedback resistance of approximately 500 kΩ B CMOS output Hysteresis input Pull up resistor optional C At an output pull up resistor P ch of approximately 50 kΩ 5 0 V not available for MB89F202 F202RA N ch open drain reset output Hysteresis input High voltage input tolerable in MB90F202RA X1 Standby control signal X0 P ch N ch P ch Input enable Port Res...

Page 31: ...output available P40 to P43 are large current drive type G CMOS output CMOS input Hysteresis input Resource input Analog input H CMOS input Table 1 8 1 I O Circuit Types 2 2 Types Circuit Remarks P ch N ch P ch Input enable Input enable Port Resource P ch N ch P ch Input enable Port P ch Open drain control Analog input A D enable N ch Input enable Port P ch Analog input A D enable N ch P ch Input ...

Page 32: ...16 CHAPTER 1 OVERVIEW ...

Page 33: ...17 CHAPTER 2 HANDLING DEVICES This chapter describes the precautions to be taken when handling general purpose one chip microcontrollers 2 1 Precautions on Handling Devices ...

Page 34: ...nge in the supply voltage within the specified range may result in a malfunction The following stabilization guidelines are recommended The Vcc ripple P P value at the supply frequency 50 Hz to 60 Hz should be less than 10 of the typical Vcc value and the transient fluctuation rate should be less than 0 1 V ms at the time of momentary fluctuation when switching the power supply Handling unused inp...

Page 35: ...during flash memory program erase The typical high voltage is 10 V Step down circuit stabilization time The MB89202 F202RA series consists of the products listed in Table 2 1 1 Pin Processing for the Products with and without a Step down Circuit The operation characteristic depends on whether a product contains a step down circuit These products use the same internal resources However the operatio...

Page 36: ...lize prior to normal operation of the step down circuit Oscillation stabilization wait time 218 FCH Power supply VCC Step down circuit stabilization time 217 FCH Oscillation stabilization wait time 218 FCH CPU operation of product with a step down circuit MB89F202 F202RA CPU operation of product without a step down circuit MB89202 and MB89V201 Start of CPU operation of product without a step down ...

Page 37: ...pter describes the functions and operations of the CPU 3 1 Memory Space 3 2 Dedicated Register 3 3 General Purpose Registers 3 4 Interrupts 3 5 Reset 3 6 Clock 3 7 Standby Mode Low Power Consumption Mode 3 8 Memory Access Mode ...

Page 38: ... to the I O area can be obtained in the same manner as access to memory Also direct addressing provides high speed access RAM area Static RAM is equipped as the internal data area The size of internal RAM depends on the model Direct addressing allows high speed access to an area from 80H to FFH Some models restrict the usable range of the area 100H to 1FFH can be used as the general purpose regist...

Page 39: ...MB89F202 F202RA RAM 512 bytes RAM 512 bytes Not available Not available Not available External EPROM 32 KB Register Register Register ROM 16 KB Flash 16 KB I O I O 0000H 0080H 0100H 0200H 0280H C000H FFFFH 0000H 0080H 0100H 0200H 0280H C000H FFFFH 0000H 0080H 0100H 0200H 0280H 8000H FFFFH ...

Page 40: ...ector Table Area Address FFC0H to FFFFH This area is used as vector tables of the vector call instructions interrupts and reset This area is allocated to the highest ranges of the ROM area and the start address of the corresponding processing routine is set to the address of each vector table Table 3 1 1 provides the reference addresses in the vector table that correspond to the vector instruction...

Page 41: ...H IRQ3 FFF4H FFF5H IRQ2 FFF6H FFF7H IRQ1 FFF8H FFF9H IRQ0 FFFAH FFFBH Mode data FFFDH Reset vector FFFEH FFFFH For MB89202 MB89V201 FFFCH is prohibited Use FFH For MB89F202 F202RA write 01H to FFFCH to activate read protection otherwise write FFH Table 3 1 1 Vector Table 2 2 Vector call instruction Address in the vector table Upper digits Lower digits ...

Page 42: ...es close to operation codes instructions and lower bytes are stored in the following addresses Operands that indicate memory addresses and 16 bit immediate data are handled in the same manner as stated above Figure 3 1 3 shows the locations of 16 bit data in instructions Figure 3 1 3 Location of 16 bit Data in Instructions 16 bit Data Storage State in Stack The upper byte of data for a 16 bit regi...

Page 43: ...cumulator is a 16 bit arithmetic operation register It handles arithmetic operations or data transfer using data on memory or data in another register such as temporary accumulator T The accumulator allows data in it to be used as a word 16 bits or bytes 8 bits When arithmetic operations or data transfer is handled in the unit of a byte only the lower 8 bits AL of the accumulator are used the uppe...

Page 44: ...offset to the index address The initial value of the index register specified after the reset operation is undefined Extra pointer EP The extra pointer is a 16 bit register Data in the extra pointer is handled as the memory address for accessing data The initial value of the extra pointer specified after the reset operation is undefined Stack pointer SP The stack pointer is a 16 bit register that ...

Page 45: ...sed for operations other than addition or subtraction Negative flag N When the highest bit becomes 1 as a result of an arithmetic operation the negative flag is set to 1 When it becomes 0 it is cleared with 0 Zero flag Z When the result of an arithmetic operation is 0 the zero flag is set to 1 Otherwise the zero flag is cleared with 0 Overflow flag V When a complement on 2 overflow occurs as a res...

Page 46: ...mally the SETI instruction sets the interrupt enable flag to 1 and the CLRI instruction sets it to 0 to clear Interrupt level bits IL1 and IL0 These bits indicate the level of an interrupt the CPU is accepting then it is compared with the values in the interrupt level setting registers ILR1 to 4 which is specified as the level of interrupt requests of peripheral functions IRQ0 to IRQF When the int...

Page 47: ... Setting a value from 0 to 31 in the upper five bits of the register bank pointer specifies a register bank One register bank contains eight 8 bit general purpose registers that are selected with the lower 3 bits of an operation code The register bank pointer allows a range of 0100H to 01FFH maximum to be used as the general purpose register area However some models restrict the usable range when ...

Page 48: ... R0 to R7 and up to 32 banks can be used However some models restrict the number of usable banks when only internal RAM is used The register bank pointer RP specifies the register bank being used The lower three bits of an operation code indicate general purpose register 0 R0 to general purpose register 7 R7 Figure 3 3 1 shows the configuration of the register banks Figure 3 3 1 Configuration of R...

Page 49: ...correctly overwritten by another routine simply specifying the specific register bank at the beginning of the interrupt processing routine stores the data contained in the general purpose registers before interruption This feature allows data in general purpose registers to avoid being put in the stack and allows interrupts to be handled efficiently at high speed For subroutine calls in addition t...

Page 50: ...of four interrupt processing intensities to be assigned to each interrupt request Interrupt requests with levels equal to or less than that of an interrupt request being handled in the interrupt processing routine are usually handled after the current interrupt processing routine ends If interrupt requests with the same assigned level are generated simultaneously IRQ0 has priority Table 3 4 1 Inte...

Page 51: ...FFE0H FFE1H LD1 LD0 IRQE Unused FFDEH FFDFH LE1 LE0 IRQF Unused FFDCH FFDDH LF1 LF0 Table 3 4 1 Interrupt Requests and Interrupt Vectors 2 2 Interrupt request Address in the vector table Names of bits in the interrupt level setting registers Priority at identical level at simultaneous occurrence Upper digits Lower digits ...

Page 52: ...n interrupt level 3 is specified the CPU does not accept interrupt requests Table 3 4 2 provides the relationship between interrupt level setting bits and interrupt levels Notes When the main program is being executed the interrupt level bits in the condition code register CCR IL1 and IL0 are normally set to 11B The ILR1 to ILR4 registers are write only enabled and thus the bit manipulation instru...

Page 53: ...ion program for peripheral functions specify interrupt levels in the interrupt level setting registers ILR1 to ILR4 concerned then start up the peripheral functions Interrupt levels 1 2 and 3 can be specified Level 1 is the highest level and level 2 is the second highest level Level 3 prohibits interrupts from the peripheral functions to which it is assigned Run the main program For a multiple int...

Page 54: ... register CCR IL1 and IL0 to the value of the interrupt level accepted and then start the interrupt processing routine Finally restore the values of the program counter PC and program status PS put into the stack with the RETI instruction then execute an instruction following the instruction executed immediately before the interruption Standby mode low power consumption mode is cancelled by an int...

Page 55: ...the condition code register CCR IL1 and IL0 are set to the same value as the value in the interrupt level setting register corresponding to the A D interrupt ILR1 2 3 or 4 i e 2 in this example If an interrupt request with a higher interrupt level specified is generated 1 in this example processing for the higher interrupt level is effected first To temporarily prohibit multiple interrupts in the ...

Page 56: ...ime After accepting an interrupt the CPU needs 9 instruction cycles for interrupt processing preparation to Save the values in the program counter PC and program status PS Set the address at the beginning of the interrupt processing routine interrupt vector into the PC Update the interrupt level bits PS CCR IL1 and IL0 in the program status PS Figure 3 4 4 shows the interrupt processing time Figur...

Page 57: ...on RETI is executed at the end of interrupt processing the values in the program status PS and the program counter PC are restored from the stack in that order which is opposite to that at the beginning of interrupt processing This operation restores the values in the PS and PC to those values used before interruption Note Values in the accumulator A and temporary accumulator T are not automatical...

Page 58: ... pointer SP indicates the highest address of RAM and that the data area be set up from the lowest address of RAM Figure 3 4 6 is an example showing the stack area Figure 3 4 6 Stack Area for Interrupt Processing Note For the stack area interrupts subroutine calls or PUSHW instruction use addresses in descending order and the return instructions RETI and RET or the POPW instruction releases address...

Page 59: ...et output pin in accordance with option settings Software reset Software reset generates a 4 instruction cycle reset by writing 0 into the software reset bit in the standby control register STBC RST Software reset does not wait until oscillation stabilization wait time has expired Watchdog reset Watchdog reset generates a 4 instruction cycle reset when no data is written into the watchdog control ...

Page 60: ...n wait time Table 3 5 2 shows the relationship between reset sources oscillation stabilization wait time and the reset operation mode fetch Table 3 5 2 Relationship between the Reset Sources and Oscillation Stabilization Wait Time Reset source Operating mode Reset operation and oscillation stabilization wait time External reset When power is turned on or stop mode The reset operation is performed ...

Page 61: ...PONR ERST WDOG SFTR XXXX B R R R R R Read only Unused X Undefined Address Initial value Software reset flag bit When read When read When read When written When written When written The source is software reset PONR 0 1 When read When written Does not affect operations Watchdog reset flag bit Does not affect operations Does not affect operations Does not affect operations The source is watchdog res...

Page 62: ...r reset flags are maintained when all other reset flags have been set before the external reset flag is set This bit is cleared with 0 after being read Writing a value to this bit has no significance bit5 WDOG Watchdog reset flag bit 1 is set to this bit when watchdog reset occurs 1 is set to this bit while other reset flags are maintained when all other reset flags have been set before the watchd...

Page 63: ...in RST generates an internal reset signal by making use of L level input The RST outputs the L level signal according to the internal reset source and oscillation stabilization wait time applied following a reset The internal reset source may be software reset watchdog reset or power on reset Note External reset input is accepted asynchronously regardless of the internal clock Initialization of th...

Page 64: ...f the Reset Operation Figure 3 5 3 Reset Operation Flow YES YES NO YES NO Software reset Watchdog reset External reset input Power on reset Power on reset selected When power is turned on or in stop mode State of reset wait ing for stabilization of oscillation External reset state cancelled Mode data fetch State of reset wait ing for stabilization of oscillation State of reset wait ing for stabili...

Page 65: ... has expired In this case if the external reset input is not cancelled the CPU performs the reset operation following cancellation of the external reset When an external clock is used oscillation stabilization wait time is applied and thus input of an external clock is required at a reset The time base timer generates oscillation stabilization wait time Influence from a Reset of Contents in RAM Wh...

Page 66: ... data from internal ROM States of Pins after the CPU Reads the Mode Data Most of the I O pins remain Hi Z immediately after the CPU reads the mode data For pin states established by something other than a reset see APPENDIX E Pin State of the MB89202 F202RA Series for details Note For pins that are Hi Z when a reset source is generated set up the devices connected with the pins such that they do n...

Page 67: ...Map The clock controller manages oscillation of the clock and provision of the clock to the CPU and peripheral circuits peripheral functions Thus the operating clock for the CPU or peripheral circuits is affected by clock speed switching gears and setting in standby mode sleep stop To peripheral functions a divided frequency output of the free run counter operating with the clock for peripheral ci...

Page 68: ...r EC pin T0 pin 8 bit PWM timer PWM pin 2 3 4 1 2 2 4 A D converter AN pin Continuous conversion Continuous conversion Conversion comparison UART prescaler Serial switch UCK SCK pin U0 S0 pin UI SI pin 8 bit serial I O Buzzer BZ pin 12 bit PPG PPG pin External interrupt 1 INT1 pin External interrupt 2 INT2 pin Oscillation stabilization wait time Instruction cycle Not affected by the gear The gear ...

Page 69: ... ceramic resonator Connect it as shown in Figure 3 6 2 Figure 3 6 2 Example of Connecting a Crystal Resonator or Ceramic Resonator For an external clock Connect it to the X0 pin and open the X1 pin as shown in Figure 3 6 3 Figure 3 6 3 Example of Connecting an External Clock X1 MB89202 F202RA series Oscillation circuit X0 X0 X1 MB89202 F202RA series Oscillation circuit Open ...

Page 70: ...Figure 3 6 4 Block Diagram of Clock Controller STP SLP SPL RST SCM WT1 WT0 CS1 CS0 214 FCH 217 FCH 218 FCH 1tINST 1tINST FCH tINST Standby control register STBC Pin control Stop Sleep Clock for time base timer 1 2 frequency Clock generator System clock selector Pre scaler 1 4 frequency 1 8 frequency 1 16 frequency 1 64 frequency Selector Clock control circuit Supplied to the CPU Supplied to periph...

Page 71: ... stop signal for the oscillation stabilization wait time selector is cancelled Oscillation stabilization wait time selector Selects one of three oscillation stabilization wait time periods generated by the time base timer according to the standby mode or a reset then outputs the clock supply stop signal to the CPU by using the selected time period System clock control register SYCC Selects the clo...

Page 72: ...0 1 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0007H WT1 SCM WT0 CS1 CS0 1 MM 00B R W R R W R W R W R Read only R W Readable Writable Unused M Mask option Initial value Address Initial value Clock speed selection bits Instruction cycle when FCH is 12 5 MHz Oscillation stabilization wait time selection bits Oscillation stabilization wait time according to output of the time base timer when FCH is 12...

Page 73: ...ts are undefined when read Writing values into these bits does not affect operation bit4 bit3 WT1 WT0 Oscillation stabilization wait time selection bits Used to select an oscillation stabilization wait time setting When external interrupt causes a return from stop mode to active mode the oscillation stabilization wait time setting selected by these bits is applied The initial values of these bits ...

Page 74: ... affect the time base timer Power consumption can be reduced by lowering the clock speed Table 3 6 2 Operations in Each Clock Mode Clock speed Standby mode Clock Operating clock in each block Cause that cancels standby mode excepting reset SYCC register SYCC CS1 and CS0 CPU time base timer Peripheral function 1 1 High speed Low speed RUN Generated FCH 4 FCH 2 FCH 4 Interrupt request Sleep Stopped ...

Page 75: ...ing gears In active mode specifying standby mode results in a transition to sleep mode or stop mode Operations always start in RUN mode after a reset any type Operating modes are cancelled by a reset Note Do not rewrite the values in the oscillation stabilization wait time selection bits SYCC WT1 and WT0 while the clock is waiting for stabilization of oscillation Using the system clock monitor bit...

Page 76: ...etting appropriate to the oscillator used must be selected Figure 3 6 6 shows changes in a frequency generated by an resonator from generation to stabilization Figure 3 6 6 Changes of a Frequency after Generation Oscillation Stabilization Wait Time Oscillation stabilization wait time is to be applied to start the clock in active mode while the clock is stopped Oscillation stabilization wait time i...

Page 77: ...abilization wait time Table 3 6 3 shows the relationship between the active mode operation start conditions and oscillation stabilization wait time Table 3 6 3 Active Mode Operation Start Conditions and Oscillation Stabilization Wait Time Active mode operation start condition When power is turned on Cancellation of stop mode External reset External interrupt Selection of oscillation stabilization ...

Page 78: ...k mode and explains block operations in standby mode Standby Mode In active mode power consumption is reduced by lowering the speed of the operating clock for the CPU and peripheral circuits using clock speed switching gears However in standby mode the clock controller stops supply of the clock to the CPU sleep mode or stops oscillation of the source stop mode to reduce power consumption Sleep mod...

Page 79: ... CPU and Peripheral Functions in Standby Mode Function RUN Sleep Stop SPL 0 Stop SPL 1 Clock Active Active Stopped Stopped CPU Instruction Active Stopped Stopped Stopped ROM Active Holding Holding Holding RAM Peripheral function I O port Active Holding Holding Hi Z Time base timer Active Active Stopped Stopped Watchdog timer Active Stopped Stopped Stopped 8 bit PWM timer counter Active Active Stop...

Page 80: ...ontinuously Even after the interrupt is processed completely transition to sleep mode is not possible Cancellation of sleep mode Sleep mode is cancelled by a reset or interrupt from a peripheral function Pin states are initialized by the reset operation When an interrupt request with an interrupt level higher than 11B is generated in a peripheral function or external interrupt circuit in sleep mod...

Page 81: ... to stop mode prohibit the time base timer interrupt request output TBTC TBIE 0 when necessary Cancellation of stop mode Stop mode is cancelled by a reset or external interrupt When a reset occurs in stop mode the reset operation is performed after oscillation stabilization wait time pin states are initialized by the reset operation When an interrupt request with an interrupt level higher than 11B...

Page 82: ...R W R W R W R R W Read only Unused Initial value R Readable Writable Address Initial value Reserved bit When read When read When read When read When written When written When written When written Always 0 Does not affect operations Software reset bit 4 instruction reset signal generated Always 1 Does not affect operations Pin state setting bit Pin states applied are maintained in stop mode Pin sta...

Page 83: ...fies external pin states in stop mode Writing 0 into this bit maintains states levels of the external pins at transition to stop mode Writing 1 into this bit sets states of the external pins to Hi Z states of pins for which a pull up resistor is specified are set to level H This bit becomes 0 after a reset bit4 RST Software reset bit This bit specifies software reset Writing 0 into this bit genera...

Page 84: ...ait reset mode Reset mode RUN mode Sleep mode Oscillation stabilization wait Stop mode 9 4 1 2 3 6 5 11 8 7 10 1 Cancellation of reset input 2 3 4 5 6 7 8 9 10 11 Reset sources multiple Transition to sleep mode by the standby control register STBC SLP 1 External reset input Transition to stop mode by the standby control register STBC STP 1 External interrupt request External reset input Interrupt ...

Page 85: ...tion stabilization wait time output of time base timer 1 Cancellation of reset input Reset in RUN mode 2 External reset software reset or watchdog reset Table 3 7 4 Transition to and Cancellation of Standby Mode State transition Transition conditions Transition to sleep mode 3 STBC SLP 1 Cancellation of sleep mode 6 Interrupt each type 4 External reset Transition to stop mode 5 STBC STP 1 Cancella...

Page 86: ... request with an interrupt level higher than 11B is generated in a peripheral function or another component in sleep mode or stop mode standby mode is cancelled This operation does not depend on whether the CPU can accept interrupts After cancellation of standby mode the CPU normally takes a branch to the interrupt processing routine if the priority of the interrupt level setting register ILR1 to ...

Page 87: ...clock oscillation stabilization wait time settings generated by the time base timer If the interval selected for the time base timer is shorter than the oscillation stabilization wait time an interval timer interrupt request is generated during oscillation stabilization wait time To prevent this from occurring disable output of time base timer interrupt requests TBTC TBIE 0 before transition to st...

Page 88: ... single chip mode Figure 3 8 1 Configuration of Mode Data Operations for Selecting Memory Access Mode Only single chip mode is selectable Table 3 8 1 provides the settings for the mode pins and mode data Figure 3 8 2 shows the operations for selecting memory access 00H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FFFDH Address Value Operation Selects single chip mode Other than 00H Reserved Do not spec...

Page 89: ...k of the mode data Setup of I O pin functions at execution of program RUN mode Source of a reset is generated I O pins are high impedance Being reset Mode data and reset vector are fetched from internal ROM Mode data Other settings Prohibited Single chip mode 00H I O settings for each I O pin using the port direction register DDR and other measures I O pins are available as ports ...

Page 90: ...74 CHAPTER 3 CPU ...

Page 91: ...TER 4 I O PORTS This chapter describes the functions and operations of I O ports 4 1 Overview of I O Ports 4 2 Port 0 4 3 Port 3 4 4 Port 4 4 5 Port 5 4 6 Port 6 4 7 Port 7 4 8 Programming Example of I O Port ...

Page 92: ...ut pin Port 4 General purpose I O port of a type switched between CMOS push pull and N ch open drain may also serve peripherals analog input pins Port 5 General purpose I O port may also serve peripherals 8 bit PWM pin Port 6 General purpose I O port for MB89F202 F202RA P61 P60 are input port Port 7 General purpose I O port Table 4 1 1 lists the functions of the ports and Table 4 1 2 lists the reg...

Page 93: ...direction register DDR4 R W 0010H 0000B Port 4 output form setting register OUT4 R W 0011H 0000B Port 5 data register PDR5 R W 0012H XB Port 5 data direction register DDR5 R W 0013H 0B Port 5 pull up setting register PUL5 R W 0072H 0B Port 6 data register PDR6 R W 0060H XXB Port 6 data direction register 2 DDR6 R W 0061H 00B Port 6 pull up setting register PUL6 R W 0062H 00B Port 7 data register P...

Page 94: ...sed as external interrupt input pins Table 4 2 1 lists the pins of port 0 For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types For pin operation when used as analog input see CHAPTER 12 A D CONVERTER Table 4 2 1 Pins of Port 0 Port name Pin name Function Peripherals for which a pin may serve Input and output form Circuit type Input Output Port 0 P00 INT20 AN4 P00 ge...

Page 95: ...port 0 registers DDR Pch Nch PDR PUL SPL Pin status setting bit of standby control register STBC SPL 1 A D converter channel select A D converter enable bit A D input occurring To A D converter s analog input External interrupt From external interrupt enable Stop mode No A D input Pull up resistor External interrupt Pins Internal data bus PDR read PDR read when read modify write is performed PDR w...

Page 96: ... to 1 the pin functions as an output port When the bit is set to 0 the pin functions as an input port Note Because the DDR0 register is write only bit manipulation instructions SETB CLRB do not apply Setting a port pin to serve external interrupt inputs If a pin of port 0 is used as an external interrupt input pin enable the external interrupt circuit operation and set the pin to function as an in...

Page 97: ...t latch of 0 is set and L level is output to the pin in output port mode R W 0000H XXXXXXXXB 1 Pin state is H level Output latch of 1 is set and H level is output to the pin in output port mode Port 0 data direction register DDR0 0 Read prohibited write only Output transistor operation is disabled and the pin is set to serve as an input pin W 0001H 00000000B 1 Output transistor operation is enable...

Page 98: ...ernal interrupt input mode Set a bit of the DDR0 register to 0 the bit corresponding to a pin of port 0 that is to serve as an external interrupt input pin to set the pin to function as an input port The value state of the pin can be read by reading the PDR0 register regardless of whether external interrupt inputs or interrupt request outputs are enabled or disabled Operation in analog input mode ...

Page 99: ...the pins of port 0 Note When the pull up resistor is selected by using the pull up setting register the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z Table 4 2 4 Operating Modes of Pins of Port 0 Pin name Normal operation sleep stop SPL 0 Stop SPL 1 At a reset P00 INT20 AN4 to P03 INT23 AN7 General purpose ...

Page 100: ...a general purpose I O port when being used for peripherals Table 4 3 1 lists the pins of port 3 For circuit type see 1 7 Pin Functions Description Table 4 3 1 Pins of Port 3 Port name Pin name Function Peripherals for which the pin may serve Input and output form Circuit type Input Output Port 3 P30 UCK SCK P30 general purpose I O UCK SCK UART clock I O 8 bit serial I O clock I O CMOS hysteresis C...

Page 101: ...abulates the correspondence between the pins and the bits of port 3 registers DDR Pch Nch PDR PUL Internal data bus PDR read PDR write PDR read when read modify write is performed Output latch DDR write PUL read PUL write External interrupt Input to peripheral Input to peripheral Output from peripheral Output from peripheral enable Stop mode SPL 1 Output occurring from peripheral External interrup...

Page 102: ...rt When the bit is set to 0 the pin functions as an input port Note Because the DDR3 register is write only bit manipulation instructions SETB CLRB do not apply Setting a port pin to serve external interrupts If a pin of port 3 is used as an external interrupt input pin enable the external interrupt circuit operation and set the pin to function as an input port When the pin is set in this mode its...

Page 103: ... of 0 is set and L level is output to the pin in output port mode R W 000CH XXXXXXXXB 1 Pin state is H level Output latch of 1 is set and H level is output to the pin in output port mode Port 3 data direction register DDR3 0 Read prohibited write only Output transistor operation is disabled and the pin is set to serve as an input pin W 000DH 00000000B 1 Output transistor operation is enabled and t...

Page 104: ...register Operation in external interrupt input mode Set a bit of the DDR3 register to 0 the bit corresponding to a pin of port 3 that is to serve as an external interrupt input pin to set the pin to function as an input port The value state of the pin can be read by reading the PDR3 register regardless of whether or not the external interrupt inputs or interrupt request outputs are enabled Operati...

Page 105: ...omes Hi Z because the output transistor is turned OFF regardless of the value existing on the DDR3 register in the bit position corresponding to the pin Table 4 3 4 summarizes the operating modes of the pins of port 3 Note When the pull up resistor is selected by using the pull up setting register the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up i...

Page 106: ...OS push pull and N ch open drain and analog input pins P40 AN0 to P43 AN3 Port 4 data register PDR4 Port 4 data direction register DDR4 Port 4 output format setting register OUT4 Pins of Port 4 Port 4 has four I O pins of CMOS push pull N ch open drain These pins can also be used as analog input pins Those pins that are used for analog inputs cannot be used as a general purpose I O port Table 4 4 ...

Page 107: ...rt 4 registers DDR Pch Nch PDR OUT Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR write Stop mode SPL 1 OUT read OUT write A D converter channel select To A D converter s analog input A D converter enable bit Pins Stop mode SPL 1 DDR read Table 4 4 2 Correspondence between the Pins and the Bits of the Port 4 Register Port name Bits of associated ...

Page 108: ...Registers Register name Data When being read When being written Read Write Address Initial value Port 4 data register PDR4 0 Pin state is L level Output latch of 0 is set and L level is output to the pin in output port mode R W 000FH XXXXB 1 Pin state is H level N ch open drain type Output latch of 1 is set and the pin in output port mode is set at Hi Z CMOS push pull type Output latch of 1 is set...

Page 109: ...set to OFF and the pin is set at Hi Z Its output latch value can be read by reading the PDR4 register Set the bit of the ADEN register of the A D converter to 1 the bit corresponding to the analog input pin in use Operation when a reset is performed When the CPU is reset the bits of the PDR4 register are initialized to 1 Thus the output transistors become OFF input port mode and the pins become Hi...

Page 110: ...ock diagram of pins and associated registers Structure of Port 5 Port 5 comprises the following four elements General purpose I O pins P50 PWM Port 5 data register PDR5 Port 5 data direction register DDR5 Port 5 pull up setting register PUL5 Pins of Port 5 Port 5 has one CMOS I O pin Table 4 5 1 provides information on the pin of port 5 For circuit type see Section 1 7 Pin Functions Description an...

Page 111: ...port 5 registers DDR P ch N ch PDR PUL Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR write PUL read Stop mode SPL 1 Output from peripheral Output enable from peripheral Pull up resistor Pin Stop mode SPL 1 PUL write DDR read Table 4 5 2 Correspondence between the Pin and a Bit of the Port 5 Registers Port name Bits of associated registers and co...

Page 112: ...d do not change Port 5 data direction register DDR5 A bit of the DDR5 register sets the I O direction of the pin corresponding to the bit When the bit of the DDR5 register is set to 1 the pin functions as an output port When the bit is set to 0 the pin functions as an input port Setting the output from a peripheral enable If a peripheral with an output pin is used set the output enable bit of the ...

Page 113: ... 5 data register PDR5 0 Pin state is L level Output latch of 0 is set and L level is output to the pin in output port mode R W 00012H XB 1 Pin state is H level Output latch of 1 is set and the pin in output port mode is set at Hi Z Port 5 data direction register DDR5 0 Input port pin The pin is set to function as an input pin with output transistor operation disabled R W 0013H 0B 1 Output port pin...

Page 114: ...Operation in mode enabling the output from a peripheral When the output enable bit for a peripheral is set enable the corresponding pin is set to serve the output from the peripheral Because the value state of the pin can be read from the PDR5 register even when the output from the peripheral is enabled the value output from the peripheral can be read Operation when a reset is performed When the C...

Page 115: ...ull up state instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z Table 4 5 4 Operating Modes of Pin of Port 5 Pin name Normal operation sleep stop SPL 0 Stop SPL 1 At a reset P50 PWM General purpose I O port further may serve I O for peripherals Hi Z Hi Z SPL Pin state setting bit of standby control register STBC SPL Hi Z High impedance ...

Page 116: ... PDR6 Port 6 data direction register DDR6 not used in MB89F202 F202RA Port 6 pull up setting register PUL6 Pins of Port 6 Port 6 has 2 I O pins of CMOS input type they are input only pins for MB89F202 F202RA Table 4 6 1 lists the pins of port 6 P61 and P60 are general purpose input port for MB89F202 F202RA For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types Table 4...

Page 117: ...te PUL read Stop mode SPL 1 Pull up resistor Pin Stop mode SPL 1 PUL write For MB89202 V201 PDR DDR Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR read Pin Stop mode SPL 1 DDR read For MB89F202 F202RA PUL PUL read PUL write DDR read SPL Pin state setting bit of standby control register STBC SPL SPL Pin state setting bit of standby control registe...

Page 118: ...rrespondence Table 4 6 2 tabulates the correspondence between the pins and the bits of the port 6 registers DDR control is not used for this bit in MB89F202 F202RA Table 4 6 2 Correspondence between the Pins and the Bits of Port 6 Registers Port name Bits of associated registers and corresponding pins Port 6 PDR6 DDR6 PUL6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Pin corresponding to bit P61 P60 ...

Page 119: ...60 P61 The DDR6 register sets the I O direction of each pin per bit When a bit of the DDR6 corresponding to a pin of port 6 is set to 1 the pin functions as an output port When the bit is set to 0 the pin functions as an input port Table 4 6 3 lists the functions of the port 6 registers Table 4 6 3 Functions of Port 6 Registers Register name Data When being read When being written Read Write Addre...

Page 120: ... instead of Hi Z during stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 6 2 shows the pull up resistor settings assigned to the values of the bits of the port 6 pull up setting register Figure 4 6 2 Pull up Resistor Settings PUL6 PUL61 PUL60 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0062H PUL61 PUL60 00B R W R W R W Address Initial value P61 pull up ...

Page 121: ...ata is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDR6 register Operation when a reset is performed When the CPU is reset the bits of the DDR6 register are initialized to 0 Thus all output transistors become OFF and the pins become Hi Z However CPU resets do not initialize the PDR6 register If a pin is used as an output port after th...

Page 122: ...ister the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z Table 4 6 4 Operating Modes of Pins of Port 6 Pin name Normal operation sleep stop SPL 0 Stop SPL 1 At a reset P60 P61 General purpose I O port Hi Z Hi Z ...

Page 123: ... comprises the following four elements General purpose I O pin P70 to P72 Port 7 data register PDR7 Port 7 data direction register DDR7 Port 7 pull up setting register PUL7 Pins of Port 7 Port 7 has 3 CMOS I O pin Table 4 7 1 lists the pins of port 7 For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types Table 4 7 1 Pins of Port 7 Port name Pin name Function Input and...

Page 124: ...dence between the pins and the bits of the port 7 registers DDR Pch Nch PDR PUL Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR write PUL read Stop mode SPL 1 Pull up resistor Pin Stop mode SPL 1 PUL write DDR read Table 4 7 2 Correspondence between the Pins and the Bits of the Port 7 Registers Port name Bits of associated registers and correspond...

Page 125: ...The DDR7 register sets the I O direction of each pin per bit When a bit of the DDR7 corresponding to a pin of port 7 is set to 1 the pin functions as an output port When the bit is set to 0 the pin functions as an input port Table 4 7 3 lists the functions of the port 7 registers Table 4 7 3 Functions of Port 7 Registers Register name Data When being read When being written Read Write Address Init...

Page 126: ...ing stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 7 2 shows the pull up resistor settings assigned to the values of the bits of the port 7 pull up register Figure 4 7 2 Pull up Resistor Settings PUL7 PUL72 PUL71 PUL70 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0065H PUL72 PUL71 PUL70 000B R W R W R W R W Address Initial value P72 pull up OFF P71 pul...

Page 127: ... the PDR7 register the written data is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDR7 register Operation when a reset is performed When the CPU is reset the bits of the DDR7 register are initialized to 0 Thus all output transistors become OFF and the pins become Hi Z However CPU resets do not initialize the PDR7 register If a pin is...

Page 128: ...y using the pull up setting register the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z Table 4 7 4 Operating Modes of Pins of Port 7 Pin name Normal operation sleep stop SPL 0 Stop SPL 1 At a reset P70 to P72 General purpose I O port Hi Z Hi Z ...

Page 129: ...3 are used to light all seven segments of LED eight segments if the decimal point is included Pin P00 is connected to the anode common pin of LED and pins P30 to P37 are connected to the pins of the segments Figure 4 8 1 provides an example of the pins and the 8 segment LED connected Figure 4 8 1 Example of the Pins and the 8 segment LED Connected P30 P36 P37 P00 MB89202 V201 F202 F202RA ...

Page 130: ...rt 3 data register DDR3 EQU 000DH Address of port 3 data direction register Main program CSEG CODE SEGMENT CLRB PDR0 0 Set P00 at L level MOV PDR3 11111111B Set all pins of port 3 at H level MOV DDR0 11111111B Set P00 to function as an output port by coding XXXXXXX1B MOV DDR3 11111111B Set all bits of DDR3 such that all pins of port 3 function as an output port ENDS END ...

Page 131: ...f the time base timer 5 1 Overview of Time base Timer 5 2 Configuration of Time base Timer 5 3 Time base Timer Control Register TBTC 5 4 Interrupt of Time base Timer 5 5 Operations of Time base Timer Functions 5 6 Notes on Using Time base Timer 5 7 Program Example for Time base Timer ...

Page 132: ...ble 5 1 1 lists the time intervals for the time base timer Clock Supply Function The clock supply function is used to provide one of three timer outputs for the oscillation stabilization wait time and the operation clock for the resource function Table 5 1 2 lists cycles of the clock that the time base timer supplies to peripherals Table 5 1 1 Time Intervals for Time base Timer Internal count cloc...

Page 133: ...ce Watchdog timer 222 FCH Approximately 335 5 ms Watchdog timer count up clock A D converter 28 FCH Approximately 20 5 µs Continuous activation clock FCH Oscillation frequency The values enclosed in parentheses are time intervals when the oscillation frequency is 12 5 MHz Table 5 1 2 Clock Cycles Supplied by Time base Timer 2 2 Clock supplied to Clock cycle Remarks ...

Page 134: ...er on reset occurs Interval timer selector Selects 1 bit for the interval timer from four bits in the time base counter When the specified bit overflows an interrupt occurs Time base timer control register TBTC Selects a time interval clears the counter controls interrupts or checks the status TB0F TBIE TBC1 TBC0 TBR OF OF OF OF FCH Oscillation frequency X21 Time base timer counter X22 X23 X26 X27...

Page 135: ...IE TBC1 TBC0 TBR 00 000B R W R W R W R W R W R W Readable Writable Initial value 215 FCH 218 FCH 222 FCH Address Initial value Time base timer initialization bit Read Read Write The time base timer counter is cleared Write 1 is always read Nothing is changed and affected Time interval selection bits FCH Oscillation frequency Interrupt request enable bit The interrupt request output is disabled The...

Page 136: ...disables an interrupt request to be output to the CPU An interrupt request is output when this bit and the overflow interrupt request flag bit TBOF are both 1 bit5 to bit3 Unused bits These bits are undefined when they are read Nothing is affected when they are written bit2 bit1 TBC1 TBC0 Time interval selection bits These bits specify a time interval for the interval timer The interval timer bits...

Page 137: ...e same time Note An interrupt request is generated immediately after the TBIE bit is set from 0 disable to 1 enable if the TBOF bit is 1 When the counter is cleared TBTC TBR 0 and the specified bit overflows at the same time the TBOF bit is not set Oscillation Stabilization Time and Time base Timer Interrupts If a time interval is set the time shorter than the oscillation stabilization time the in...

Page 138: ...ation stabilization time is measured from when the time base timer counter is cleared to when the oscillation stabilization bit overflows One of three oscillation stabilization time can be selected by the oscillation stabilization time selection bits of the system clock control register SYCC WT1 WT0 The time base timer supplies clocks to the watchdog timer and A D converter Clearing the time base ...

Page 139: ...tart Interval cycle TBTC TBC1 TBC0 11B Counter clear Power on reset optional Cleared by interrupt handling routine TBOF bit TBIE bit Sleep SLP bit STBC register Exit stop state by IRQ7 Stop STP bit STBC register Exit stop state by an external interrupt Note When the interval time selection bits of time base timer control register TBTC TBC1 TBC0 are set to 11 222 FCH Oscillation stabilization time ...

Page 140: ...cillation has not yet started in stop mode or when the power is turned on Therefore the time base timer makes oscillation stabilization wait time after the resonator starts operating The appropriate oscillation stabilization time must be selected according to the type of resonator connected to the resonator clock generator See Section 3 6 1 Clock Generator Notes on peripheral functions the time ba...

Page 141: ...Definition of interrupt request flag bit ILR2 EQU 007CH Address of interrupt level setting register 2 INT_V DSEG ABS DATA SEGMENT ORG 0FFECH IRQ7 DW WARI Setting interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP or other registers are assumed to have been initialized CLRI Interrupt disable MOV ILR2 01111111B Setting interrupt level level 1 MOV TBTC 01000100B Clearing inte...

Page 142: ...126 CHAPTER 5 TIME BASE TIMER POPW A RETI ENDS END ...

Page 143: ...ctions and operations of the watchdog timer 6 1 Overview of Watchdog Timer 6 2 Configuration of Watchdog Timer 6 3 Watchdog Control Register WDTC 6 4 Operations of Watchdog Timer Functions 6 5 Notes on Using Watchdog Timer 6 6 Program Example for Watchdog Timer ...

Page 144: ...chdog reset occurs following the time between the minimum time interval and the maximum time interval The counter must be cleared before the time of the minimum time interval See Section 6 4 Operations of Watchdog Timer Functions for details on the maximum and minimum time intervals of the watchdog timer Notes The watchdog timer counter is cleared when the time base counter is cleared TBTC TBR 0 w...

Page 145: ...tes by accepting output from the time base timer as the count clock Reset control circuit Sends the reset signal to the CPU when the watchdog timer counter overflows Counter clear control circuit Controls the clearing and stopping of the watchdog timer counter Watchdog control register WDTC Activates and clears the watchdog timer counter Because this register is write only bit manipulation instruc...

Page 146: ...second or subsequent writing after a reset Other than above No operation Reserved bit Write 0 to this bit Unused R W Readable writable X Undefined Table 6 3 1 Explanation of Functions of Each Bit in Watchdog Control Register WDTC Bit name Description bit7 RESV Reserved bit Write 0 to this bit bit6 to bit4 Unused bits Undefined when it is read Writing values does not affect operation bit3 to bit0 W...

Page 147: ...When the counter is not cleared within the time interval of the watchdog timer the counter overflows and the timer generates the internal reset signal having a period of four instruction cycles Time intervals of watchdog timer The time interval varies depending on the timing at which the watchdog timer is cleared Figure 6 4 1 shows the relationship between the clear timings and time intervals of t...

Page 148: ...er Clearing the time base timer counter that supplies the count clock to the watchdog timer also clears the watchdog timer counter at the same time Switching to sleep or stop mode clears the watchdog timer counter Notes on creating programs When creating a program that repeatedly clears the watchdog timer in the main loop ensure that the time necessary for main loop processing including interrupt ...

Page 149: ...operating at 12 5 MHz of the watchdog timer Coding example WDTC EQU 0009H Address of watchdog control register WDT_CLR EQU 00000101B VECT DSEG ABS DATA SEGMENT ORG 0FFFEH RST_V DW PROG Setting reset vector VECT ENDS Main program CSEG CODE SEGMENT PROG Initialization routine upon reset MOVW SP 0280H Setting initial value of stack pointer for interrupt Initializing interrupt or other peripheral func...

Page 150: ...134 CHAPTER 6 WATCHDOG TIMER ...

Page 151: ...7 2 Configuration of 8 bit PWM Timer 7 3 Pin of 8 bit PWM Timer 7 4 Registers of 8 bit PWM Timer 7 5 Interrupt of 8 bit PWM Timer 7 6 Operations of the Interval Timer Functions 7 7 Operations of the 8 bit PWM Timer Functions 7 8 States in Each Mode During Operation 7 9 Notes on Using 8 bit PWM Timer 7 10 Program Example for PWM Timer ...

Page 152: ...evel of the pin P50 PWM pin can be inverted for each interrupt the square wave of any frequency can also be output An interval timer operation from the cycle of the count clock to 28 times cycle is possible The count clock can be selected from four types Table 7 1 1 shows the range of intervals and square wave output Table 7 1 1 Range of Intervals and Square Wave Output Count clock cycle Interval ...

Page 153: ...can be output at a duty ratio of 0 to 99 6 The frequency of the PWM wave can be selected from four types The low pass filter can be connected to the output and used as the D A converter Table 7 1 2 shows the frequency of the PWM wave that can be set by PWM timer functions Figure 7 1 1 is a configuration example of the D A converter 1 4 FCH COMR register value 1 4 12 5 MHz 221 1 71 0 µs Output freq...

Page 154: ... Filter Note While PWM timer functions are enabled no interrupt request occurs Va Vcc TH T Va C R Va T TL TH Tr Vcc Vcc PWM output Analog output Va PWM pin Analog output waveform Relationship between analog output voltage and PWM output waveform Tr represents the amount required to stabilize output PWM output waveform t ...

Page 155: ... register CNTR Block Diagram of an 8 bit PWM Timer Figure 7 2 1 Block Diagram of an 8 bit PWM Timer tINST Instruction cycle P TX P1 P0 TPE TIR OE TIE CLK ECLK 1 16 64 1t INST CNTR COMR IRQ9 TO P50 PWM 8 8 Internal data bus PWM compare register Output of an 8 16 bit capture timer counter Count clock selector 8 bit counter Start Clear Latch Overflow Comparator Timer PWM PWM generation circuit and ou...

Page 156: ...t request occurs And when the bit to control the output pin CNTR OE is 1 the output level of the P50 PWM pin is inverted by the output control circuit at which time the 8 bit counter is cleared During the PWM timer operation once a match is detected the output level of the P50 PWM pin is changed from H level to L level by the PWM generation circuit Thereafter when the 8 bit counter overflows the o...

Page 157: ...ile the pin functions as the PWM timer the PWM wave is output to the pin When the bit to control the output pin is set to the dedicated pin CNTR OE 1 the P50 PWM pin automatically functions as an output pin regardless of the value of the port 5 data direction register DDR5 bit0 and as the PWM pin Block Diagram of the Pin Related to the 8 bit PWM Timer Figure 7 3 1 Block Diagram of the Pin Related ...

Page 158: ...use the PWM compare register COMR is a write only register an instruction to operate bits cannot be used bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0022H P TX P1 P0 TPE TIR OE TIE 0 000000B R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0023H XXXXXXXXB W W W W W W W W R W W X CNTR PWM control register Address Initial value COMR PWM compare register Initial value Readable Writable...

Page 159: ...tial value Bit to enable an interrupt request Disables interrupt request output Enables interrupt request output Bit to control the output pin Used as the general purpose port P50 Used as the output pin for the interval timer or PWM timer PWM Interrupt request flag bit Read Write The interval timer used The PWM timer used The counter value does not match the settings Not changed Clears this bit Th...

Page 160: ...unctions To start the count operation write 1 to this bit When 0 is written to this bit the counter is cleared setting 00H and then stopped bit2 TIR Interrupt request flag bit While the internal timer functions are enabled When the counter value matches the PWM compare register COMR value 1 is set to this bit When this bit and the bit to enable an interrupt request TIE are 1 an interrupt request t...

Page 161: ... interval in the register to which the value compared with the counter value is to be set When the settings written to this register match the counter value the counter is cleared and 1 is set to the interrupt request flag bit CNTR TIR 1 If a value is written to the COMR register while the counter is operating the value takes effect at the next cycle after detection of a match Note The settings of...

Page 162: ...PWM pin When a match is found L is output until the counter value overflows If a value is written to the COMR register while the counter is operating the value takes effect at the next cycle after overflow Note The settings and cycle of the COMR register while the PWM timer is operating can be calculated using the following formula The gear function however affects the instruction cycle COMR regis...

Page 163: ... to the TIR bit using the interrupt handling routine to clear the interrupt request The TIR bit is set to 1 when the counter value matches the settings regardless of the value of the TIE bit Note When a match is found between the counter value and the COMR register value concurrently with the stop of the counter CNTR TPE 0 the TIR bit is not set When the TIR bit is 1 if the TIE bit is changed from...

Page 164: ... counter is activated the counter is incremented from 00H at the start up of the selected count clock When the counter value matches the value set in the COMR register comparison value the timer inverts the level of the PWM pin clears the counter sets the interrupt request flag bit CNTR TIR 1 and starts incrementing again from 00H at the next start up of the count clock Figure 7 6 2 shows the oper...

Page 165: ...r functions are enabled the output level of the PWM pin in the counter stop state CNTR TPE 0 is at L level FFH FFH 80H FFH 80H 00H FFH 80H Counter value Comparison value Timer cycle Change of the COMR value Time COMR value Clear in the program TIR bit TPE bit OE bit PWM pin When the bit to control the output pin OE is 0 the pin functions as a general purpose I O port pin P50 If the PWM compare reg...

Page 166: ... counter is activated the counter is incremented from 00H at the start up of the selected count clock The output PWM waveform of the PWM pin is H until a match between the counter value and the value set in the COMR register is found Once a match is found the output is L until the counter value overflows FFH 00H Figure 7 7 2 shows the PWM waveform output to the PWM pin bit7 bit6 bit5 bit4 bit3 bit...

Page 167: ...ions are enabled the level immediately before the stop is held as the output level of the PWM pin in the counter stop state CNTR TPE 0 FFH 00H 00H L H 00H FFH 00H FFH 00H 80H L H L H 00H When the COMR Register Value is 00H 0 duty ratio Counter value PWM waveform When the COMR register value is 80H 50 duty ratio When the COMR register value is FFH 99 6 duty ratio Counter value PWM waveform Counter ...

Page 168: ...spend request occurs the counter value status in which interval timer functions are enabled is shown in the Figure 7 8 1 and the counter value status in which PWM timer functions are enabled is shown in the Figure 7 8 2 When switched to the stop mode the counter holds a value and stops When the stop mode is released by an external interrupt the counter starts operation from the held value Therefor...

Page 169: ... stabilization Time Clear by the program Stopping operation Restarting operation TIR bit TPE bit PWM pin OE 1 L level while operation is being stopped SLP bit STBC register Sleep Release of sleep by IRQ9 Stop STP bit STBC register Release of stop by an external interrupt When the bit to specify the pin state STBC SPL of the standby control register is 1 and the PWM pin is not pulled up the PWM pin...

Page 170: ...ing operation SLP bit STBC register Sleep Release of sleep by something other than IRQ9 IRQ9 does not occur STP bit STBC register Stop Time to wait for oscillation stabilization Release of stop by an external interrupt When the bit to specify the pin state STBC SPL of the standby control register is 1 and the PWM pin is not pulled up the PWM pin in the stop mode is Hi Z When the SPL bit is 0 the v...

Page 171: ... do not change the count clock cycle CNTR P1 P0 If the user wants to switch between the interval timer function and the PWM timer function CNTR P TX proceed when the counter is stopped CNTR TPE 0 interrupts are disabled CNTR TIE 0 and interrupt requests are cleared CNTR TIR 0 When the interrupt request flag bit CNTR TIR is 1 and the bit to enable an interrupt request is enabled CNTR TIE 1 recovery...

Page 172: ...nables the PWM output 1 4 instruction cycle Depending on the port state Executing the instruction to enable PWM output L H MOV CNTR 11001000B Starts PWM operations internal clocks and count operations Uses the general purpose port Check MOV CNTR 11001010B Enables PWM output Check Depending on the port state Executing the instruction to enable the PWM output ...

Page 173: ...0023H Address of the PWM compare register TPE EQU CNTR 3 Defining the bit to enable the counter operation TIR EQU CNTR 2 Defining the interrupt request flag bit ILR3 EQU 007D Address of the register to set the interrupt level INT_V DSEG ABS DATA SEGMENT ORG 0FFF8H IRQ9 DW WARI1 Setting the interrupt vector INT_V ENDS Main program CSEG CODE SEGMENT The stack pointer SP and others are assumed to hav...

Page 174: ...158 CHAPTER 7 8 BIT PWM TIMER User processing POPW A XCHW A T Restoring A and T POPW A RETI ENDS ...

Page 175: ...50 is shown below COMR register value 50 100 256 128 080H Coding example CNTR EQU 0022H Address of the PWM control register COMR EQU 0023H Address of the PWM compare register TPE EQU CNTR 3 Defining the bit to enable the counter operation Main program CSEG CODE SEGMENT CLRB TPE Stopping the counter operation MOV COMR 80H Specification of the H level width of a pulse 50 duty ratio MOV CNTR 10011010...

Page 176: ...160 CHAPTER 7 8 BIT PWM TIMER ...

Page 177: ...ns of 8 16 bit Capture Timer Counter 8 4 Registers of 8 16 bit Capture Timer Counter 8 5 8 16 bit Capture Timer Counter of Interrupts 8 6 Explanation of Operations of Interval Timer Functions 8 7 Operation of Counter Functions 8 8 Functions of Operations of Capture Functions 8 9 8 16 bit Capture Timer Counter Operation in Each Mode 8 10 Notes on Using 8 16 bit Capture Timer Counter 8 11 Program Ex...

Page 178: ...eries to serve as a 16 bit timer Interval Timer Function The interval timer function generates interrupt requests repeatedly at any time interval This function can also invert the output level of P34 TO INT10 pin per time interval and output square waves of any frequency In the 8 bit mode the interval timer function operates as two independent timers timer 0 8 bit capture timer counter and timer 1...

Page 179: ...215tINST 1 28tINST to 1 216tINST 256tINST 28 tINST to 216 tINST 1 29 tINST to 1 217 tINST 512tINST 29 tINST to 217 tINST 1 210 tINST to 1 218 tINST External clock 1text 1text to 28text 1 2text to 1 29text Table 8 1 2 Timer 1 Interval Time and Square Wave Output Range in 8 bit Mode Count clock cycle Interval time Square wave output range Hz Internal count clock 2tINST 2tINST to 29 tINST 1 22 tINST ...

Page 180: ...trol register SYCC Table 8 1 3 Interval Time and Square Wave Output Range in 16 bit Mode Count clock cycle Interval time Square wave output range Hz Internal count clock 2tINST 2tINST to 217 tINST 1 22 tINST to 1 218 tINST 4tINST 22 tINST to 218 tINST 1 23 tINST to 1 219 tINST 16tINST 24 tINST to 220 tINST 1 25 tINST to 1 221 tINST 64tINST 26 tINST to 222 tINST 1 27 tINST to 1 223 tINST 128tINST 2...

Page 181: ...e 16 bit mode The counter function counts the number of edges of the external clocks selected by the count clock selection bit CINV of the timer 0 control register TCR0 When the number of edges equals the setting value the counter function generates an interrupt request and inverts the output level of the square wave output pin In timer 0 for the 8 bit mode a count operation up to 28 is possible I...

Page 182: ...agram of 8 16 bit Capture Timer Counter Counter clear mask capture clr Counter clear mask identity clr Counter clear Capture latch Internal data bus 8 bit mode Port output enable Timer0 Timer1 output selection CK0 TDR0 TDR1 TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 CK6 to to CO CK EQ CLR Q TFF EQ CLR CK CK6 CK0 3 3 CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDG...

Page 183: ...generated In this case if square wave output is allowed the corresponding output control circuit inverts the output of the square wave output pin Timer 0 1 data registers TDR0 TDR1 TDR0 and TDR1 are used to set the data to be compared with each 8 bit counter value at write Timer 0 1 control registers TCR0 TCR1 TCR0 and TCR1 are used to select functions allow and prohibit operations control interru...

Page 184: ...his pin is also used as an input pin When using this pin as the EC pin set 0 in the port data 3 direction register DDR3 bit3 and set the output transistor to OFF to enable the EC pin to be used as an input port P34 TO INT10 pin The P34 TO INT10 pin shares functions of the general purpose I O port P34 and the square wave output pin for the timer TO It also shares a function of the input pin for ext...

Page 185: ... the stop mode SPL 1 becomes high pull up state not Hi Z During the reset however pull up becomes ineffective and the pin state becomes Hi Z DDR P ch N ch EC PDR INT10 PUL P34 TO INT10 P33 EC P33 EC P34 TO INT10 External interrupt allowed Internal data bus PDR read Resource input Stop mode SPL 1 Resource output enable Resource output available Pull up resistor PDR read At read modify write Output ...

Page 186: ...7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001CH XXXXXXXXB R W R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001DH XXXXXXXXB R W R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001EH XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001FH XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0020H PEN TSEL 00B R W R W R W R X TCCR cap...

Page 187: ...it Operation is not affected at all Capture mode enable edge detection selection bit Capture input prohibition Operation in timer counter mode Falling edge selection Rising edge selection Selection of both falling and rising edges Operation in capture mode Compare match counter clear mask bit The counter is cleared per compare match The counter is not cleared at compare match Counter clear mask bi...

Page 188: ...tput when this bit and the capture edge detection flag bit CPIF are 1 bit4 CCMSK Counter clear mask bit at capture operation The counter state when a capture match is detected is set When this bit is 0 the counter is cleared When this bit is 1 the counter is not cleared bit3 TCMSK Compare match counter clear mask bit The counter state when a compare edge is detected is set When this bit is 0 the c...

Page 189: ... R W R W R W R W R W R W R W R W Readable Writable R Read only Initial value 1 1 TSTR0 Address Initial value Timer start bit The counter operation is stopped The counter is cleared and increment starts Clock source selection bits oscillation 12 5 MHz External clock Count clock selection bit The counter is incremented at the falling edge of a selected clock source The counter is incremented at the ...

Page 190: ...ed even if this bit is set to 0 bit5 T0IEN Interrupt request enable bit This bit is used to allow and prohibit interrupt request output to the CPU An interrupt request is output when this bit and the interrupt request enable bit T0IEN are 1 bit4 CINV Count clock selection bit This bit is used to select whether to increment the counter at the rising or falling edge of a clock When this bit is 0 the...

Page 191: ...t3 bit2 bit1 bit0 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 R R W R W R W R W R W R W R W Readable Writable R Read only Initial value 1 1 1 Address Initial value Timer start bit The counter operation is stopped The counter is cleared and increment is started Clock source selection bits oscillation 12 5 MHz 16 bit mode Interrupt request enable bit Interrupt request output is prohibited Interrupt req...

Page 192: ...ven if this bit is set to 0 bit5 T1IEN Interrupt request enable bit This bit is used to allow and prohibit interrupt request output to the CPU An interrupt request is output when this bit and the interrupt request enable bit T0IEN are 1 bit4 Not used This bit is undefined at read At write this bit does not affect operation bit3 to bit1 TCS12 TCS11 TCS10 Clock source selection bits These bits are u...

Page 193: ...tput enable bit The P34 TO INT10 pin acts as the general purpose port P34 The P34 TO INT10 pin acts as the square wave output pin of the 8 16 bit capture timer counter 0020H 00B Table 8 4 4 Explanation of Functions of Each Bit in Timer Output Control Register TCR2 Bit name Function bit7 to bit2 Unused bits At read the values of these bits are undefined At write these bits do not affect operation b...

Page 194: ...t When the count operation is allowed TCR0 TSTR0 0 1 the value in TDR0 is set in loaded to the comparator data latch and the counter is incremented When the values in the comparator data latch match those in the counter as a result of the increment the values in the TDR0 are reset in the comparator data latch the counter is cleared and the count operation is continued The comparator data latch is ...

Page 195: ...unction is used the lower 8 bits of the count value to be detected are set The values in TDR0 are loaded to the lower 8 bits of the comparator data latch when matching the counter values of the 16 bit timer or when the count operation is started The values written to TDR0 when the 16 bit counter is in operation become valid after match detection For the values set in TDR1 when the interval timer f...

Page 196: ...counter When the interval timer function is used an interval timer value is set When the counter function is used the count value to be detected is set The values in TDR1 are reset in loaded to the comparator data latch when they match the values in the counter or when the count operation is started The values written to TDR1 when the counter is operating become valid from the next cycle after mat...

Page 197: ...the counter values of the 16 bit timer or when the count operation is started The values written to TDR1 when the 16 bit counter is operating become valid after match detection In the 16 bit mode the count operation is controlled by the timer 0 control register TCR0 Note The values set in TDR0 and TDR1 when the interval function is used can be calculated from the expression shown below However the...

Page 198: ...its in the 16 bit capture mode In the read operation in the timer counter mode counter values are read Capture Data Registers H and L TCPH and TCPL The number of events detected in the capture mode is stored in TCPH and TCPL Data cannot be written to these registers because the registers are read only Figure 8 4 8 shows the bit structures of capture data registers H and L Figure 8 4 8 Bit Structur...

Page 199: ...arator data latch timer 0 data register TDR0 corresponding to the timer 0 data register TDR0 the compare match detection flag bit TCR0 TIF0 is set to 1 In this case when the interrupt request flag bit is allowed when TCR0 T0IEN 1 timer 0 generates an interrupt request IRQ3 to the CPU Set the TFCR0 bit to 1 and clear the interrupt request with the interrupt processing routine When the counter value...

Page 200: ... than or equal to 0001H or 01H The 8 16 bit capture timer counter also cannot generate an interrupt if the counter function detects the 0000H or 00H width Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts For interrupt operation see Section 3 4 2 Steps in the Interrupt Operation Table 8 5 2 Register and Vector Table Related to 8 16 bit Capture Timer counter of Inter...

Page 201: ... set as shown in Figure 8 6 1 Figure 8 6 1 Setting of Interval Timer Function Timer 0 To operate timer 1 as the interval timer function in the 8 bit mode the function must be set as shown in Figure 8 6 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCCR CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TCR1 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 TCR0 TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0 TCR2 PEN...

Page 202: ...ut is allowed TCR2 PEN and timer 0 is set to output selection TCR2 TSEL 0 a square wave is output from the timer output pin TO If the counter value matches the value set in the data register when timer 1 is being used the output of the square wave output control circuit toggles When square wave output is allowed TCR2 PEN and timer 1 is set to output selection TCR2 TSEL 1 a square wave is output fr...

Page 203: ...ue TDR0 value E0H E0H FFH 1 Time Clear by program TIF0 bit Counter clear 2 Start Match Match Match TSTR0 bit TO pin 1 If the data register is rewritten when the counter is in operation the interval timer function becomes valid from the next cycle When timer 0 is started or when a match is detected the counter is cleared and the values in the data register are loaded to the comparator data latch ...

Page 204: ... of TDR1 and the lower 8 bits of TDR0 16 bits in total The values are compared with the 16 bit counter value The 16 bits of the counter are cleared at the same time Other operations in the 16 bit mode are the same as timer 0 operation in the 8 bit mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCCR CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TCR1 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 TCR0 TIF0 ...

Page 205: ... function timer 0 in 8 bit mode operation except that the external clock is used instead of the internal clock The number of events can be known by reading the capture data register TCPL A specific number of events can be known by the event count detection function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DDR3 0 TCCR CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TCR1 TIF1 TFCR1 T1IEN TCS12 TCS11 TC...

Page 206: ...sed In this case a compare match does not cause data to be re loaded to the compare latch To update the compare latch value stop and restart the timer Figure 8 7 2 shows counter function operation in the external clock mode in which TCMSK is used Figure 8 7 2 Counter Function Operation in External Clock Mode 00H 01H 02H 03H 7EH 7FH 00H 01H 00 7F 00H 01H 02H 03H 7EH 7FH 80H 81H 00 TFCR0 1 W 7FH 7FH...

Page 207: ...he internal clock Figure 8 7 4 shows counter function operation in 16 bit mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DDR3 0 TCCR CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TCR1 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 TCR0 TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0 1 1 1 TCR2 PEN TSEL TDR1 TDR0 TCPH TCPL Used bit Unused bit 0 Set 0 1 Set 1 1 1 1 Setting of 00 Setting of the higher 8 bits o...

Page 208: ...lock Counter clear TSTR0 bits Counter value Comparator data latch 1 lower 8 bit comparison value Comparator data latch 2 higher 8 bit comparison value Load Load TDR0 lower 8 bit setting value TDR1 higher 8 bit setting value Data setting 1234H TIF0 Clear by program A value can be set according to any timing When the counter is started or when a match is detected the data register setting value is l...

Page 209: ...ts TCS02 TCS01 and TCS00 of the timer 0 control register TCR0 have been set In the capture mode the count value is captured to the capture data register TCPL each time a capture input edge is detected and the capture edge detection flag CPIF is set to 1 In this case if the capture interrupt enable bit CPIEN is already set to 1 an interrupt request is output to the CPU The capture mode is divided i...

Page 210: ...te The capture input pin also serves as the external clock input pin The external clock mode cannot be used in the capture mode Table 8 8 1 shows the relationship between the counter mode and the compare latch operation according to the clear mask bit value Table 8 8 1 Relationship between Counter Mode and Compare Latch Operation CCMSK TCMSK Counter mode Data load to compare latch and counter clea...

Page 211: ...TER Figure 8 8 2 Capture Mode Operation TDR0 0000H TSTR0 FFFFH TIF0 CPIF CCMSK 0 TCMSK 0 CCMSK 1 TCMSK 1 CCMSK 1 TCMSK 0 EQ CAP CAP Counter clear Compare latch Count value Capture latch Capture input EC TFCR0 1 W TFCR0 1 W CFCLR 1 W CFCLR 1 W ...

Page 212: ...number of detected events are stored in the capture data register H TCPH and the lower 8 bits are stored in the capture data register L TCPL For operation in the 16 bit mode see operation in the 8 bit mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DDR3 0 TCCR CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TCR1 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 TCR0 TIF0 TFCR0 T0IEN CINV TCS02 TCS01 TCS00 TSTR0...

Page 213: ...etained value and so the first interval time and external clock count are incorrect When the stop mode is released the 8 16 bit capture timer counter must be initialized When the counter is temporarily stopped TSTR0 0 it retains its value and stops If the subsequent operation is continued TSTR0 1 the count value is cleared and the counter is restarted Figure 8 9 1 Counter Operation in Standby Mode...

Page 214: ...a value other than 111B in the count clock selection bits TCS12 TCS11 TCS10 of the timer 1 control register TCR1 Using timer 0 without setting 111B results in a malfunction Note on setting by program When using the 8 16 bit capture timer counter in the 16 bit mode set the count clock selection bits TCS12 TCS11 TCS10 of TCR1 to 111B Before using the counter values when the counter is in operation w...

Page 215: ...pture mode no external clock can be selected set the count clock bits TCS12 TCS11 and TCR1 TCS10 to a value other than 111B Note on using interrupts If the compare register value is 0000H or 00H the 8 16 bit capture timer counter cannot generate interrupts For this reason when using interrupts set a value greater than or equal to 0001H or 01H The 8 16 bit capture timer counter cannot generate inte...

Page 216: ... control register TCR0 EQU 001BH Address of timer 0 control register TCR2 EQU 0020H Address of timer output control register TDR1 EQU 001CH Address of timer 1 data register TDR0 EQU 001DH Address of timer 0 data register TIF0 EQU TCR0 7 Defines the timer 0 interrupt request flag bit ILR1 EQU 007BH Address of interrupt request setting register INT_V DSEG ABS DATA SEGMENT ORG 0FFF0H IRQD DW WARI Set...

Page 217: ...from the P34 pin MOV TCR0 10101011B Allows timer 0 interrupt request output clears the counter and starts the timer SETI Enables the CPU interrupt Interrupt program WARI CLRB TIF0 Clears the interrupt request flag PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END ...

Page 218: ... level setting register 2 INT_V DSEG ABS DATA SEGMENT ORG 0FFF0H IRQD DW WARI Sets the interrupt vector ENDS Main program CSEG CODE SEGMENT The stack pointer SP etc is already initialized MOV DDR3 00000000B Sets the EC pin to input CLRI Disables the interrupt MOV ILR1 10111111B Sets the interrupt level to 2 MOV TDR0 088H Sets the counter value and the lower 8 bits of the compare value MOV TDR1 013...

Page 219: ...W A BNE READ16 Jumps to re read when a mismatch is detected RET16 RET Restarts the count operation and begins counting 10 000 pulses Interrupt program WARI CLRB TIF0 Clears the interrupt request flag PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END ...

Page 220: ...204 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER ...

Page 221: ...of a 12 bit PPG timer 9 1 Overview of 12 bit PPG Timer 9 2 Configuration of 12 bit PPG Timer Circuit 9 3 Pin of 12 bit PPG Timer 9 4 Registers of 12 bit PPG Timer 9 5 Operations of 12 bit PPG Timer Functions 9 6 Notes on Using 12 bit PPG Timer 9 7 Program Example for 12 bit PPG Timer ...

Page 222: ...and H width are variable Note An example of calculating the output pulse cycle period and H width as executed by a 12 bit PPG function is given below When an oscillation FCH of 12 5 MHz and a count clock cycle period of 2 tINST are set and if Compare value for cycle period 011110B 30 clock period Compare value for H width 001010B 10 clock width Then H width and the cycle period of output pulse wav...

Page 223: ...ble 9 1 2 lists available resolution values minimum step duty cycles and output pulse cycle periods 10 2 0 32 µs Cycle period Compare value for cycle period Count clock cycle period 011110H 30 clock period 2 4 FCH 30 2 0 32 µs 19 2 µs H width Compare value for H width Count clock cycle period 001010B 10 clock width 2 4 FCH 6 4 µs Table 9 1 2 Resolutions and Output Pulse Cycle Periods Supported whe...

Page 224: ...00 tINST 1 1000 0 1 2000 1 to 2000 4000 tINST 8000 tINST 32000 tINST 512000 tINST 1 2000 0 05 3000 1 to 3000 6000 tINST 12000 tINST 48000 tINST 768000 tINST 1 3000 0 03 4095 1 to 4095 8190 tINST 16380 tINST 65520 tINST 1048320 tINST 1 4095 0 02 tINST Instruction cycle Table 9 1 2 Resolutions and Output Pulse Cycle Periods Supported when the Timer is Used as a 12 bit PPG 2 2 Compare value for cycle...

Page 225: ...2 bit PPG control register 4 RCR24 Block Diagram of 12 bit PPG Timer Figure 9 2 1 Block Diagram of 12 bit PPG Timer Instruction cycle RCK1 RCK0 HSC5 HSC4 HSC3 HSC2 HSC1 HSC0 HSC11 HSC10 HSC9 HSC8 HSC7 HSC6 SCL11 SCL10 SCL9 SCL8 SCL7 SCL6 RCEN SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 CLK 2 4 16 256 12 12 1t INST RCR21 RCR22 RCR24 RCR23 tINST Internal data bus Count clock selector 12 bit counter Clear Comparat...

Page 226: ...unter has been synchronized with the value of the register containing the compare value for H width The comparator then maintains outputs at L until a count by the counter is synchronized with the value of the register containing the set cycle period At this time the 12 bit counter is cleared and restarts to count from 00H 12 bit PPG control registers 1 RCR21 and 2 RCR22 These registers comprise b...

Page 227: ...it PPG Timer The pin associated with the 12 bit PPG timer is P37 BZ PPG pin P37 BZ PPG pin This pin functions as a CMOS type P37 general purpose I O port further functioning as 12 bit PPG timer output PPG PPG By setting the output enable bit of the appropriate 12 bit PPG control register RCR23 RCEN to 1 the pin functions as the PPG output pin through which the set cycle period and H width of PPG p...

Page 228: ...the H level pull up state in stop mode SPL 1 Because buzzer outputs to the P37 BZ PPG pin precede 12 bit PPG outputs to this pin if the pin is used as the PPG pin turn the buzzer outputs off and set the RCEN bit such that PPG outputs are enabled DDR P ch N ch PDR PUL P37 BZ PPG Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR write PUL read PUL wri...

Page 229: ...4 bit3 bit2 bit1 bit0 0015H HSC11 HSC10 HSC9 HSC8 HSC7 HSC6 000000B R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0016H RCEN SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 0 000000B R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0017H SCL11 SCL10 SCL9 SCL8 SCL7 SCL6 000000B R W R W R W R W R W R W R W Readable and Writable Unused RCR21 12 bit PPG control register 1 Address In...

Page 230: ...Writable Initial value Address Initial value H width setting bits Compare value for the H width of 12 bit PPG outputs Count clock selection bits Table 9 4 1 Explanation of Functions of Each Bit in 12 bit PPG Control Register 1 RCR21 Bit name Function bit7 bit6 RCK1 RCK0 Count clock selection bits These bits are used to select a count clock of the 12 bit PPG timer from four types of internal count ...

Page 231: ...sed Address Initial value H width setting bits Compare value for the H width of 12 bit PPG outputs Table 9 4 2 Explanation of Functions of Each Bit in 12 bit PPG Control Register 2 RCR22 Bit name Function bit7 bit6 Unused bits Bit value is undefined when being read Written value does not affect other operations bit5 to bit0 HSC11 to HSC6 H width setting bits These bits are used to set the number o...

Page 232: ...CR23 Figure 9 4 4 12 bit PPG Control Register 3 RCR23 SCL5 to SCL0 XXXXXX RCEN 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0016H RCEN SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 0 000000B R W R W R W R W R W R W R W R W Address Initial value Cycle period setting bits Compare value for the cycle period of 12 bit PPG output Output enable bit Output disabled counter cleared Output enabled with count operation star...

Page 233: ...hen 0 is written for this bit the counter is cleared and its operation stops when 1 is written the count operation starts Even if PPG outputs are enabled by this bit setting buzzer outputs if enabled have priority bit6 Unused bit Bit value is undefined when being read Written value does not affect other operations bit5 to bit0 SCL5 to SCL0 Cycle period setting bits These bits are used to set the n...

Page 234: ...re value for the cycle period of 12 bit PPG outputs Unused Table 9 4 4 Explanation of Functions of Each Bit in 12 bit PPG Control Register 4 RCR24 Bit name Function bit7 bit6 Unused bits Bit value is undefined when being read Written value does not affect other operations bit5 to bit0 SCL11 to SCL6 Cycle period setting bits These bits are used to set the number of counts corresponding to the cycle...

Page 235: ...tion with the selected count clock and the PPG pin is maintained at H level until a count by the counter is synchronized with the compare value for the H width The PPG pin is then maintained at L level until a count by the counter is synchronized with the compare value for the cycle period At this time the 12 bit counter is cleared and restarts counting from 000H Because the H width and cycle peri...

Page 236: ...nt by counter Cycle period setting H width setting Cycle period 1 H width 2 PPG output pulse waveform 1 If internal count clock cycle period is 2 4 16 or 256 tINST cycle period compare value for cycle period multiplied by the count clock cycle period 2 If internal count clock cycle period is 2 4 16 or 256 tINST H width compare value for the H width multiplied by the count clock cycle period ...

Page 237: ...G control registers 3 and 4 RCR23 SCL5 to SCL0 and RCR24 SCL11 to SCL6 If the H width is equal to or greater than the cycle period H level outputs are always delivered through the PPG pin Resolution When the cycle period is set at 111111111111B FFFH a maximum H width resolution of 1 4095 is obtained This resolution is reduced as the cycle period setting becomes smaller and limited to a minimum of ...

Page 238: ...art Figure 9 6 2 Error before Count Operation Start RCR23 24 SCL0 to SCL11 RCR21 22 HSC0 to HSC11 FFF H 3 2 1 1 00 H Overflow Cycle period setting H width setting Count by counter Extend by overflow 1 period PPG output pulse waveform Because the count interval of the operating counter is less than the changed setting the setting is effective only within the cycle 1 2 Because a cycle period less th...

Page 239: ...z 30 The compare value for the H width of the PPG output pulse giving the duty cycle of approx 33 is determined as below At this time the H width is about 3 µs Compare value for the H width RCR21 HSC5 to HSC0 and RCR22 HSC11 to HSC6 33 100 Compare value for the cycle period 0 33 30 10 Coding example RCR21 EQU 0014H Address of 12 bit PPG control register 1 RCR22 EQU 0015H Address of 12 bit PPG cont...

Page 240: ...224 CHAPTER 9 12 BIT PPG TIMER ...

Page 241: ...e 10 1 Overview of External Interrupt Circuit 1 10 2 Configuration of External Interrupt Circuit 1 10 3 Pins of External Interrupt Circuit 1 10 4 Registers of External Interrupt Circuit 1 10 5 Interrupt of External Interrupt Circuit 1 10 6 Operations of External Interrupt Circuit 1 10 7 Program Example for External Interrupt Circuit 1 ...

Page 242: ...operating state main clock operation mode External interrupt pins Three pins P34 TO INT10 to P36 INT12 External interrupt triggering Input of a signal with an optionally selected edge or edges rising and or falling edges to one of the above external interrupt pins triggers an external interrupt Interrupt control Interrupt request outputs are enabled or disabled according to the content of an inter...

Page 243: ...rcuit 1 Figure 10 2 1 Block Diagram of External Interrupt Circuit 1 EIC1 EIC2 EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 EIR2 SL21 SL20 EIE2 P34 TO INT10 P35 INT11 10 01 11 10 01 11 P36 INT12 10 01 11 Pin Edge detecting circuit 1 Pin Selector Edge detecting circuit 0 Selector External interrupt 1 control register 1 EIC1 Interrupt request IRQ0 Interrupt request IRQ1 Internal data bus Edge detecting ci...

Page 244: ... interrupt circuit 1 to generate an interrupt request IRQ0 When a signal with an edge or edges corresponding to the selected edge polarity is input to the INT10 pin for external interrupt circuit 1 if interrupt request outputs are enabled EIC1 EIE0 1 external interrupt circuit 1 generates an IRQ0 interrupt request IRQ1 When a signal with an edge or edges corresponding to the selected edge polarity...

Page 245: ...t any time P35 INT11 and P36 INT12 pins These pins function as a general purpose I O dedicated port P35 P36 and may also serve external interrupt inputs hysteresis inputs INT11 INT12 If by the port data direction register DDR3 these pins are set to function as an input port only they also function as external interrupt input pins INT11 INT12 When external interrupt 1 control registers 1 and 2 EIC1...

Page 246: ...pin state will be H level pull up state rather than Hi Z during stop mode SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z DDR N ch PDR SPL 1 INT10 INT11 INT12 PUL P34 TO INT10 P35 INT11 P36 INT12 P ch PDR P34 TO INT10 P35 INT11 P36 INT12 Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR write PUL read PUL write Stop m...

Page 247: ...egisters Associated with External Interrupt Circuit 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0024H EIR1 SL11 SL10 EIE1 EIR0 SL01 SL00 EIE0 00000000B R W R W R W R W R W R W R W R W INT11 INT10 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0025H EIR2 SL21 SL20 EIE2 0000B R W R W R W R W INT12 R W Readable Writable Unused EIC1 External interrupt 1 control register 1 Address Address Initial value Initial ...

Page 248: ...quest enable bit 0 Disables interrupt request outputs Enables interrupt request outputs Edge polarity selection bits 0 Edge detection OFF Rising edge Falling edge Both edges External interrupt request flag bit 0 When being read When being written Signal input with specified edge or edges not detected This bit is cleared Signal input with specified edge or edges detected No change does not affect o...

Page 249: ...s or disables interrupt request outputs to CPU When this bit and external interrupt request flag bit 1 EIR1 are 1 the interrupt request is output Notes When using the external interrupt pin write 0 for bit5 of the port data direction register DDR3 so that the pin serves inputs only Regardless of the interrupt request enable bit state the state of the external interrupt pin can be read directly fro...

Page 250: ...t pin write 0 for bit4 of the port data direction register DDR3 so that the pin serves inputs only Write 0 for bit1 of the timer output control register TCR2 for the 8 16 bit capture timer counter to set the port input function on Regardless of the interrupt request enable bit state the state of the external interrupt pin can be read directly from the port data register PDR3 Table 10 4 1 Explanati...

Page 251: ...1 SL20 0 0 0 1 1 0 1 1 EIR2 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0025H EIR2 SL21 SL20 EIE2 0000B R W R W R W R W R W Readable Writable Initial value Unused Address Initial value Interrupt request enable bit 2 Disables interrupt request outputs Enables interrupt request outputs Edge polarity selection bits 2 Edge detection OFF Rising edge Falling edge Both edges External interrupt request fl...

Page 252: ... an edge or edges of a signal pulse that triggers an interrupt when the signal is input to the INT12 external interrupt pin When these bits provide a value of 00B edge detection is not performed and interrupt requests are not generated These bits may specify 01B indicating a rising edge 10B a falling edge or 11B both edges to be detected Note If edge is selected while edge detection is OFF edge de...

Page 253: ...rity selection bits the occurring input is held as is before entry to the internal edge detecting circuit If edge is selected during the edge detection OFF state edge detection may be performed unconditionally with the external interrupt request flag bit set to 1 When interrupts are set enabled EIC1 EIC2 EIE0 to EIE2 1 after the release from the reset state clear the appropriate external interrupt...

Page 254: ...When changing edge polarity for INT10 to INT12 always write 0 for the appropriate EIR bit to prevent unintended interrupt generation Table 10 5 1 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table Interrupt designation Interrupt level setting register Vector table address Register Bit for setting level Upper Lower IRQ0 ILR1 007BH L01 bit1 L00 bit0 FFFAH ...

Page 255: ... Figure 10 6 1 Setting External Interrupt Circuit 1 When the polarity of an edge or edges of a signal input from one of the external interrupt pins 1 INT10 to INT12 matches the selected edge polarity for the pin stored in the appropriate external interrupt control register EIC1 EIC2 SL00 to SL21 one of the external interrupt request flag bits EIC1 EIC2 EIR0 to EIR2 corresponding to the pin is set ...

Page 256: ...rrupt 1 INT10 Note Even when the pin is used as an external interrupt input pin the pin state can be read directly from the port data register PDR3 Pulse waveform input to INT10 pin Cleared when EIE0 bit is set Cleared by program Interrupt request flag bit is cleared by the program EIR0 bit EIE0 bit SL01 bit SL00 bit IRQ0 Edge detection OFF Rising edge Falling edge Both edges ...

Page 257: ...interrupt request flag bit SL01 EQU EIC1 2 Definition of edge polarity selection bits SL00 EQU EIC1 1 Definition of edge polarity selection bits EIE0 EQU EIC1 0 Definition of interrupt request enable bit INT_V DSEG ABS DATA SEGMENT ORG 0FFFAH IRQ1 DW WARI Interrupt vector INT1 setting INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP is assumed to have been initialized CLRI Disable interr...

Page 258: ...242 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END ...

Page 259: ...vel 11 1 Overview of External Interrupt Circuit 2 11 2 Configuration of External Interrupt Circuit 2 11 3 Pins of External Interrupt Circuit 2 11 4 Registers of External Interrupt Circuit 2 11 5 Interrupt of External Interrupt Circuit 2 11 6 Operations of External Interrupt Circuit 2 11 7 Program Example for External Interrupt Circuit 2 ...

Page 260: ...hereby enabling recovery from standby mode and a transition to normal operating state main clock operation mode External interrupt pins Eight pins P00 INT20 AN4 to P03 INT23 AN7 P04 INT24 to P07 INT27 External interrupt triggering Input of an L level signal to one of the above external interrupt pins triggers an external interrupt Interrupt control An external interrupt 2 control register EIE2 ena...

Page 261: ... external interrupt input enable bits IE20 to IE27 enable or disable L level input from the external interrupt pins with each bit corresponding to a pin External interrupt 2 flag register EIF2 The external interrupt request flag bit IF20 is used to hold or clear an interrupt request signal Trigger causing external interrupt circuit 2 to generate an interrupt IRQA When an L level signal is input to...

Page 262: ...0 at any time P04 INT24 to P07 INT27 These external interrupt pins function as external interrupt input pins hysteresis input and also serving as the pins of the general purpose I O port The P04 INT24 to P07 INT27 pins function as external interrupt input pins INT24 to INT27 if set to function as an input port by the corresponding bits of the port 0 data direction register DDR0 and if external int...

Page 263: ...ull up is invalid and the pin remains at Hi Z DDR P ch N ch PDR PUL Internal data bus PDR read PDR read when read modify write is performed Output latch PDR write DDR write PUL read PUL write To A D converter s analog input A D converter channel select A D converter enable bit From external interrupt enable Stop mode SPL 1 Stop mode SPL 1 Pull up resistor Pins SPL Pin status setting bit of standby...

Page 264: ...errupt enable bits are associated with the external interrupt pins as listed in Table 11 3 2 Table 11 3 2 Correspondence between the External Interrupt Enable Bits and the External Interrupt Pins Register Bit name External interrupt pin EIE2 bit7 IE27 INT27 bit6 IE26 INT26 bit5 IE25 INT25 bit4 IE24 INT24 bit3 IE23 INT23 bit2 IE22 INT22 bit1 IE21 INT21 bit0 IE20 INT20 ...

Page 265: ...nal Interrupt Circuit 2 Figure 11 4 1 Registers Associated with External Interrupt Circuit 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0036H IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 00000000B R W R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0037H IF20 0B R W R W Readable Writable Unused EIE2 External interrupt 2 control register Address Initial value EIF2 External interrupt 2 f...

Page 266: ...4 bit3 bit2 bit1 bit0 0036H IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20 00000000B R W R W R W R W R W R W R W R W R W Readable Writable Initial value Address Initial value External interrupt request enable bits Disables external interrupt request outputs Enables external interrupt request outputs Table 11 4 1 Correspondence between the Bits of the External Interrupt 2 Control Register EIE2 and the Ext...

Page 267: ...external interrupt inputs When the bit is set to 0 the corresponding pin functions as a general purpose port but does not accept external interrupt inputs Notes When using a pin as an external interrupt pin write 0 in the port 0 data direction register DDR0 in the bit corresponding to the pin so that the pin serves inputs only Regardless of the external interrupt input enable bit state the state o...

Page 268: ...n the bit does not affect other operations Readable Writable Unused Initial value Table 11 4 3 Explanation of Functions of Each Bit in External Interrupt 2 Flag Register EIF2 Bit name Function bit7 to bit1 Unused bits Bit value is undefined when being read The written value does not affect other operations bit0 IF20 External interrupt request flag bit When an L level signal is input to one of the ...

Page 269: ...t to the external interrupt pin continues as it is even if the IF20 bit is cleared with external interrupt inputs to the pin remaining enabled the IF20 bit is immediately set to 1 again Disable external interrupt inputs to the pin or remove the cause of the external interrupt as required Notes When enabling interrupts to the CPU following a release from the reset state clear the IF20 bit in advanc...

Page 270: ... 1 Figure 11 6 1 Setting External Interrupt Circuit 2 When an L level signal is input to an external interrupt pin among the pins INT20 to INT27 with external interrupt inputs being enabled by one of the IE20 to IE27 bits corresponding to the pin external interrupt circuit 2 generates and issues an IRQA interrupt request to the CPU Figure 11 6 2 shows the operation of external interrupt circuit 2 ...

Page 271: ...read directly from the port 0 data register PDR0 RETI RETI PDR0 bit0 Pulse waveform input to INT20 AN4 pin Detection of the L level External interrupt input enabled state Clear the bit within interrupt processing routine IRQA state also changes accordingly EIE2 IE20 EIF2 IF20 Interrupt processing Interrupt processing Operation of interrupt processing routine for IRQA Can be read at any time ...

Page 272: ...flag register IF20 EQU EIF2 0 Definition of the external interrupt request flag bit ILR3 EQU 007DH Address of the interrupt level setting register INT_V DSEG ABS DATA SEGMENT ORG 0FFE6H IRQA DW WARI Interrupt vector setting INT_V ENDS Main program CSEG CODE SEGMENT Stack pointer SP is assumed to have been initialized CLRI Disable interrupts CLRB IF20 Clear external interrupt request flag MOV ILR2 ...

Page 273: ...257 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END ...

Page 274: ...258 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL ...

Page 275: ... A D converter 12 1 Overview of A D Converter 12 2 Configuration of A D Converter 12 3 Pins of A D Converter 12 4 Registers of A D Converter 12 5 Interrupt of A D Converter 12 6 Operations of A D Converter Functions 12 7 Notes on Using A D Converter 12 8 Program Example for A D Converter ...

Page 276: ...t to 10 bit digital values An analog input can be selected from eight channels The conversion speed is 38 instruction cycles when the main clock oscillation frequency is 12 5 MHz the speed is 12 2 µs When A D conversion is completed an interrupt occurs Software can determine that the conversion has been completed To activate A D conversion functions follow one of the methods given below Activation...

Page 277: ...iagram of the A D Converter Figure 12 2 1 Block Diagram of the A D Converter RESV4 RESV3 ADCK ADIE RESV2 EXT RESV1 ANS2 ANS1 ANS0 ADI ADMV RESV0 AD TO FCH ADDH ADDL IRQ8 A D control register 2 ADC2 TO output of an 8 16 bit timer output of a time base timer 28 FCH Clock selector Analog channel selector Sample hold circuit Comparator Control circuit Internal data bus A D data register D A converter ...

Page 278: ...e following function For A D conversion functions this circuit determines the values in turn from the MSB in the 10 bit A D data register toward the LSB based on the large and small signals from the comparator When the conversion is completed it sets the interrupt request flag bit ADC1 ADI A D data register ADDH and ADDL The high order 2 bits of 10 bit A D data are stored in the ADDH register The ...

Page 279: ... AN0 pins can be used as general purpose I O ports P03 to P00 and P43 to P40 and as analog inputs AN7 to AN0 AN7 to AN0 When A D conversion functions are used input the analog voltage to be converted to these pins To enable a pin as the analog input set 1 to the bit that corresponds to the A D enable register ADEN set 0 to the bit that corresponds to the port data direction register DDR0 and switc...

Page 280: ...log input To an external interrupt From disabling an external interrupt PDR read PDR read Stop mode SPL 1 At read modify write Pull up resistor Internal data bus Output latch PDR write DDR write Pins PUL read PUL write Stop mode SPL 1 P00 INT20 AN4 P01 INT21 AN5 P02 INT22 AN6 P03 INT23 AN7 DDR Pch Nch PDR OUT P40 AN0 P41 AN1 P42 AN2 P43 AN3 A D converter channel select A D converter enable bit To ...

Page 281: ...RESV2 EXT RESV1 0000001B R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0032H XXB R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0033H XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0034H ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 00000000B R W R W R W R W R W R W R W R W R W Readable Writable R Read only Unused X Undefined ADC1 A D control register 1 Address Init...

Page 282: ... Address Initial value A D conversion activation bit This bit is enabled only when software is activated ADC2 EXT 0 Always 0 for at reading A D conversion functions are not activated A D conversion functions are activated Reserved bit Not changed This does not affect others Converting flag bit Not changed This does not affect others Not during conversion During conversion Interrupt request flag bi...

Page 283: ...errupt request ADC2 ADIE are 1 an interrupt request is output At write this bit is cleared with 0 When 1 is set to this bit nothing is changed or affected by this bit2 ADMV Convertion flag bit This bit indicates that A D conversion is being performed when A D conversion functions are enabled During conversion comparison this bit is set to 1 Note This bit is read only The written value is ignored a...

Page 284: ...adable Writable Unused Initial value Address Initial value Reserved bit Be sure to write 1 to this bit Bit for enabling continuous activation Enables activation by setting the AD bit in the ADC1 register Enables continuous activation through the clock selected in the ADCK bit Reserved bit Be sure to write 0 to this bit Enabling an interrupt request bit Disables the interrupt request output Enables...

Page 285: ...capture timer counter TO 16 bit mode is selected bit3 ADIE Enabling an interrupt request bit This bit is used to enable and disable the output of an interrupt to the CPU When this bit and the interrupt request flag bit ADC1 ADI are 1 an interrupt request is output bit2 RESV2 Reserved bit This bit is a reserved bit Be sure to write 0 to this bit bit1 EXT Bit for enabling continuous activation This ...

Page 286: ... When A D conversion functions are enabled When A D conversion is activated after about 38 instruction cycles the data on the conversion results are fixed and stored to these registers Therefore after A D conversion read these registers conversion results write 0 to the ADI bit bit3 in the ADC1 register until the next A D conversion is completed and clear the flags after A D conversion During A D ...

Page 287: ...used to select the port that corresponds to the analog input Set 1 to the corresponding bit in the ADEN register for the port to be used for analog input This prevents the DC pass when the middle level voltage is applied to the A D input port When this register is to be used as the A D input port do not select the bit that indicates use of a pull up resistor from the pull up setting register 0 1 b...

Page 288: ...ng the routine for interrupt handling to clear the interrupt request The ADI bit is set when A D conversion is completed irrespective of the value of the ADIE bit Note When the ADI bit is 1 if the ADIE bit is enabled changed from 0 to 1 an interrupt request occurs immediately Register and Vector Table Related to the Interrupt of the A D Converter See Section 3 4 2 Steps in the Interrupt Operation ...

Page 289: ...en A D conversion is activated the operations of A D conversion functions are started In addition even during conversion A D conversion functions can be reactivated Continuous activation To activate A D conversion functions continuously set registers as shown in Figure 12 6 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADC1 ANS2 ANS1 ANS0 ADI ADMV RESV0 AD 1 ADC2 RESV4 RESV3 ADCK ADIE RESV2 EXT RESV1 ...

Page 290: ...le hold circuit 2 During about 16 instruction cycles the voltage of the analog input is captured and held in the capacitor for internal sample hold This voltage is held until A D conversion has been completed 3 The comparator compares the voltage captured and held in the capacitor for sample hold with the reference voltage for A D conversion from the MSB to the LSB The results are transferred to t...

Page 291: ...ing using a program When A D conversion functions are enabled the values in the ADDH and ADDL registers are held without being changed until the activation of A D conversion However once A D conversion is activated the values in the ADDH and ADDL registers become undefined immediately When A D conversion functions are enabled do not reselect an analog input channel ADC1 ANS3 to ANS0 Especially dur...

Page 292: ...ency or clock speed gear functions affects the conversion speed of A D conversion functions Input clock of continuous activation The output of an 8 16 bit capture timer counter is affected by gear functions The output of a time base timer is not affected by gear functions Clearing a time base timer affects cycles Since the output of an 8 16 bit capture timer counter is the output of the 16 bit mod...

Page 293: ...es the AN0 analog input ADI EQU ADC1 3 Defines the interrupt request flag bit ADMV EQU ADC1 2 Defines the conversion in progress flag bit AD EQU ADC1 0 Defines the bit for activating A D conversion software activation EXT EQU ADC2 1 Defines the bit for enabling continuous activation Main program CSEG CODE SEGMENT SETB AN0 Sets the P40 AN0 pin to the analog input CLRI Disables interrupts SETB ADE0 ...

Page 294: ...278 CHAPTER 12 A D CONVERTER MOV A ADDL Reads A D conversion data low order 8 bits MOV A ADDH Reads A D conversion data high order 2 bits ENDS END ...

Page 295: ...apter describes the functions and operations of UART 13 1 Overview of UART 13 2 Configuration of UART 13 3 Pins of UART 13 4 Registers of UART 13 5 Interrupt of UART 13 6 Operations of UART Functions 13 7 Program Example for UART ...

Page 296: ... to be selected Also external clock input and 8 bit PWM timer output allow user defined baud rates to be specified The length of data is variable When no parity is used 7 bits to 9 bits are available When parity is used 6 bits to 8 bits are available Table 13 1 1 The data transfer format is NRZ Non Return to Zero Table 13 1 2 provides the transfer rates of the dedicated baud rate generator and Tab...

Page 297: ...cated baud rate generator is used 1 2 n 1 1 2 1 8 1 16 1 64 tINST 2 SMDE CS1 CS0 CR UCK 1 2 1 3 1 4 1 5 1 2 1 4 1 1 13 UART prescaler When RC2 and RC1 1 the divider is 1 even in asynchronous mode PWM output Serial clock PR2 to PR0 RC2 to RC0 tINST Instruction cycle Table 13 1 2 Transfer Cycles and Transfer Rates Available for the Dedicated Baud Rate Generator when FCH 12 5 MHz Transfer rate µs bau...

Page 298: ...al Clock is Selected Value of baud rate 1 Clock gear selected 4 FCH 8 FCH 16 FCH 64 FCH Clock divider selected PR2 PR1 PR0 Divided by 1 2 2 5 3 4 or 5 Baud rate selected RC2 RC1 RC0 Divided by 1 2 4 8 16 or 32 Synchronous asynchronous mode selected SMDE Divided by 1 or 13 Note When RC2 is 1 and RC1 is 1 the divider is 1 Clock rate CR Divided by 1 or 8 Table 13 1 3 Transfer Cycles and Transfer Rate...

Page 299: ... 0 1 COMR 0 2 64 CR 1 Table 13 1 4 Transfer Cycles and Transfer Rates Selectable for the 8 bit PWM Timer PWM timer count clock cycle Asynchronous transfer mode Synchronous transfer mode Divider for clock Transfer rate bps Divider for clock Transfer rate bps 1tINST CR 0 16 97656 to 763 2 781k to 6 1k CR 1 64 24414 to 191 16tINST CR 0 16 6103 to 47 8 2 48828 to 381 5 CR 1 64 1526 to 11 9 64tINST CR ...

Page 300: ...CS1 0 RC2 to 0 P30 UCK SCK P31 UO SO P32 UI SI RIE TIE IRQ6 RP TP IRQ5 PR2 1 0 PREN Control bus Pin Baud rate generator Transmission clock Reception control circuit Reception interrupt UART interrupt Transmission control circuit Transmission interrupt Received byte counter Transmitted byte counter Start bit detection circuit Parity transmission timing UART prescaler Reception clock Parity Parity S...

Page 301: ...TD8 TP bit Clock generator The clock generator generates the transmit receive clock in accordance with the dedicated baud rate generator external clock and 8 bit PWM timer output Reception control circuit The reception control circuit consists of the received byte counter start bit detection circuit and received parity handling circuit The received byte counter takes count of received data When a ...

Page 302: ...abled SSD RIE 1 Transmission When data to be transmitted is written into the SODR register sent to the internal shift register and the next data then becomes writable the transmission interrupt request IRQ5 is generated if the transmission interrupt request is allowed SSD TIE 1 UART prescaler baud rate generator clock divider selection register The clock input to the baud rate generator is changea...

Page 303: ...as the UART clock input pin disable clock output SMC SCKE 0 and set it as the input port using the corresponding port direction register DDR3 bit0 0 In this case be sure to select the external clock SRC CS1 and CS0 00B P31 UO SO This port functions as the general purpose I O port P31 UART serial data output pin UO or 8 bit serial data output pin SO When serial data output is enabled SMC SOE 1 this...

Page 304: ... pull up state in stop mode SPL 1 However the pull up resistor is not applied during reset accordingly the pin status becomes Hi Z DDR Pch Nch UCK PDR PUL P30 UCK SCK P32 UI SI UI P30 UCK SCK P31 UO SO Pin P32 UI SI Internal data bus PDR read PDR read At read modify write PDR write DDR write PUL read PUL write Resource output Resource output enable Stop mode SPL 1 Resource output allowed Pull up r...

Page 305: ...bit3 bit2 bit1 bit0 002BH XXXXXXXXB R R R R R R R R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 002BH XXXXXXXXB W W W W W W W W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 002CH PREN PR2 PR1 PR0 0010B R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 003BH SSEL 0B R W R W Readable Writable R Read only W Write only Unused X Undefined Address Address Address Address Address Address Address Initial val...

Page 306: ... bit0 0028H PEN SBL MC1 MC0 SMDE SCKE SOE 00000 00B R W R W R W R W R W R W R W R W Readable Writable Unused Initial value 1 1 1 Address Initial value Serial data output enable bit General purpose port or 8 bit serial I O data output pin UART serial data output pin Clock output enable bit General purpose port or clock input pin for UART 8 bit serial I O UART clock output pin Synchronization mode s...

Page 307: ...ad out from this bit is undefined Writing a value into this bit does not affect any operations bit1 SCKE Clock output enable bit This bit controls I O of the serial clock When this bit is 0 P30 UCK SCK pin functions as the serial clock input pin When this bit is 1 it functions as the serial clock output pin Notes When the UCK pin functions as the serial clock input pin SCKE 0 set the P30 UCK SCK p...

Page 308: ...5 1 6 625k 1 1 1 102 9766 12 8 78k CS1 CS0 0 16 0 0 1 64 1 0 16 0 1 1 64 2 1 0 0 1 1 1 8 1 CR 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0029H CR CS1 CS0 RC2 RC1 RC0 011000B R W R W R W R W R W R W R W Address Initial value Baud rate selection bits Asynchronous µs baud Synchronous µs baud Clock input selection bits Clock input CR bit Clock frequency divider Asynchronous Synchronous External clock...

Page 309: ...as the clock input the baud rate is set to 1 16 or 1 64 of the corresponding clock frequency depending on the CR value This bit is not significant in synchronous transfer mode bit4 bit3 CS1 CS0 Clock input selection bits These bits select the clock input The clock input can be an external clock UCK pin 8 bit PWM timer or dedicated baud rate generator bit2 to bit0 RC2 RC1 RC0 Baud rate selection bi...

Page 310: ...Detects odd parity Detects even parity Bit 8 receiving data Bit 8 transmitting data parity bit Parity used SMC PEN 1 Parity not used SMC PEN 0 Adds odd parity Adds even parity Sets bit 8 transmitting data Reception interrupt request enable bit Disables output of reception interrupt requests Enables output of reception interrupt requests Transmission interrupt request enable bit Disables output of ...

Page 311: ... serial data output pin UO When this bit and transmission interrupt request enable bit TIE are 1 the transmission interrupt request is output bit4 TIE Transmission interrupt request enable bit This bit enables or disables the transmission interrupt request to the CPU When this bit and transmission data flag bit TDRE are 1 the transmission interrupt request is output bit3 RIE Reception interrupt re...

Page 312: ...of serial input data obtained from the received data flag bit RDRF and error flag bit ORFE Figure 13 4 5 Receiving Status RDRF ORFE 0 0 0 1 1 0 1 1 Initial value Received data flag bit Overrun Framing error flag bit No data Framing error Normal data Overrun error previous data remaining ...

Page 313: ...a received is transmitted to the SIDR When the received data is correctly stored in this register 1 is set for the received data flag bit RDRF If the reception interrupt request is allowed the reception interrupt is generated When the RDRF bit has been checked in interrupt processing or the program and the received data has been stored into this register read the contents in this register after re...

Page 314: ...rts it into the serial format then outputs it from the serial data output pin UO pin When the transmitted data is written into the SODR register the transmitted data flag bit is cleared with 0 After the transmitted data is sent to the transmission shift register the transmitted data flag bit is set to 1 the data transmitted next then becomes writable At this time if the transmission interrupt requ...

Page 315: ...PC PR2 PR1 PR0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 PREN 0 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 002CH PREN PR2 PR1 PR0 0010B R W R W R W R W R W Address Initial value Clock divider selection bits Divider Divides the clock by 1 Divides the clock by 2 Divides the clock by 2 5 Divides the clock by 3 Divides the clock by 4 Divides the clock by 5 Do not specify this setting Do not specify...

Page 316: ...se bits does not affect any operation bit3 PREN UART prescaler operation enable bit Enables disables operation of the prescaler that creates the UART reference clock by dividing the oscillation frequency When this bit is 1 the UART prescaler supplies the reference clock that corresponds to the frequency selected using the oscillation frequency selection bit to the baud rate generator When this bit...

Page 317: ...it3 bit2 bit1 bit0 003BH SSEL 0B R W R W Address Initial value Serial switch bit Sets UART Sets 8 bit serial I O Readable Writable Unused Initial value Table 13 4 5 Description of the Serial Switch Register SSEL Bits Bit name Description bit7 to bit1 Unused bits The values read out from these bits are undefined Writing values to these bits does not affect any operations bit0 SSEL Serial switch bit...

Page 318: ...2 CHAPTER 13 UART Figure 13 4 10 Block Diagram of Serial Switch Register UART Internal data bus 8 bit serial I O SSEL bit SSEL register Selector Selector Port 3 Pin P30 UCK SCK Pin P32 UI SI Pin P31 UO SO ...

Page 319: ...t the RDRF bit is set to 1 If an overrun error or framing error occurs the ORFE bit is set to 1 These bits are set when a stop bit is detected If the reception interrupt is enabled SSD RIE 1 an interrupt request to the CPU IRQ6 is generated When operating mode is 2 For both RDRF and ORFE data is received or transmitted with the final data bit D8 set to 1 these flags go on when the stop bit at the ...

Page 320: ...evel specified number of data bits are transferred with LSB first then data transfer is ended with the stop bit H level Figure 13 6 1 shows the relationship between the transmit receive clock and transferred received data when operating mode 0 without parity used two stop bits synchronous transfer mode and transferred data 01001101B 8 bits are specified Note that Figure 13 6 1 does not apply to th...

Page 321: ...ired in UART operating mode 0 1 2 or 3 Figure 13 6 2 Operating Mode 0 1 2 or 3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SMC PEN SBL MC1 MC0 SMDE SCKE SOE SRC CR CS1 CS0 RC2 RC1 RC0 SSD RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP SIDR SODR DDR3 SSEL SSEL 0 0 Stores received data Writes data to be transmitted Used bit Set 0 For MC1 and MC0 set 00B in mode 0 01B in mode 1 10B in mode 2 and 11B in mode 3 ...

Page 322: ...mes writable 1 is set to the TDRE bit then an interrupt request to the CPU is generated if the transmission interrupt is allowed SSD TIE 1 Transmission Operations in Operating Mode is 0 1 2 or 3 Figure 13 6 3 shows the transmission operations when operating mode is 1 parity is not used and the number of stop bits is 1 Figure 13 6 3 Transmission Operations in Operating Mode 0 1 2 or 3 STOP START ST...

Page 323: ...p bit is detected after data is fully received If the reception interrupt is enabled SSD RIE 1 an interrupt request to the CPU IRQ6 is generated When the RDRF bit goes on the received data has been transmitted to the SIDR register In operating mode 2 when the RIE bit is 1 RDRF bit or ORFE bit is 1 and reception interrupt pin is 1 the mode 2 UART reception interrupt request is output to the CPU Not...

Page 324: ...r initialization is cancelled due to a reset time for 11 shift clock cycles is required to initialize the internal controller Therefore be sure to enable the UART prescaler operation PREN 1 using the oscillation frequency register after a reset ORFE STOP START 0 1 2 3 4 5 6 7 RDRF 1 Data reception buffer full Reception interrupt ORFE STOP START 0 1 2 3 4 5 6 7 RDRF 0 Data Reception interrupt ...

Page 325: ...lags go on when the stop bit at the end is detected However when the framing error occurs the flag goes on regardless of the final data bit An interrupt request to the CPU is generated when the flag goes on and interrupt request is enabled If the reception interrupt is enabled SSD RIE 1 an interrupt request to the CPU IRQ5 is generated When the RDRF bit goes on the received data is transmitted to ...

Page 326: ...initialization is cancelled due to a reset time for 11 shift clock cycles is required to initialize the internal controller Therefore be sure to enable the UART prescaler operation PREN 1 using the oscillation frequency register after a reset ORFE STOP START 0 1 2 3 4 5 6 7 8 RDRF 0 Data Reception interrupt ...

Page 327: ... address SMC EQU 0028H Serial mode control register address SRC EQU 0029H Serial rate control register address SSD EQU 002AH Serial status and data register address SIDR EQU 002BH Serial input data register address SODR EQU 002BH Serial output data register address UPC EQU 002CH Clock divider selection register address ILR2 EQU 007CH Interrupt level setting register address INT_V DSEG ABS DATA SEG...

Page 328: ...and enable the reception interrupt request MOV A SSD Required before transmission TDRE 1 enables transmission MOV A SIDR Clear error flags MOV SODR 13H Write the data to be transmitted 13H SETI Enable instruction Interrupt processing routine WARI PUSHW A Save A and T XCHW A T PUSHW A MOV A SSD Read the data to be transmitted then clears the input data flag MOV A SIDR User defined process POPW A Re...

Page 329: ...it Serial I O 14 3 Pins of 8 Bit Serial I O 14 4 Registers of 8 Bit Serial I O 14 5 Interrupt of 8 Bit Serial I O 14 6 Operations of Serial Output Functions 14 7 Operations of Serial Input Functions 14 8 8 Bit Serial I O Operation in Each Mode 14 9 Notes on Using 8 Bit Serial I O 14 10 Example of 8 Bit Serial I O Connection 14 11 Program Example for 8 Bit Serial I O ...

Page 330: ... function switching circuit must be used to switch the 8 bit serial I O and UART For more information on the serial function switching circuit see Section 13 4 7 Serial Switch Register SSEL Selecting the 8 bit serial I O with this serial function switching circuit enables P30 UCK SCK to be used as the serial clock I O pin SCK of the serial I O and P31 UO SO to be used as the data output pin SO Thi...

Page 331: ...ck Diagram of 8 bit Serial I O D0 to D7 D7 to D0 D7 to D0 P32 UI SI P31 UO SO 2tINST 8tINST 32tINST SST BDS CKS0 CKS1 SOE SCKE SIOE SIOF IRQC P30 UCK SCK 2 tINST Internal data bus MSB first Transfer direction selection LSB first Pin Pin Pin Shift direction Serial data register SDR Output buffer Output allowance Output allowance Shift clock selection Shift clock control circuit Serial mode register...

Page 332: ...mpleted the counter overflows When the counter overflows the serial I O transfer start bit of the SMR SST 0 is cleared and the interrupt request flag bit SIOF 1 is set When serial transfer stops SST 0 the counter stops its count It is cleared when serial transfer is started SST 1 Serial data register SDR The SDR retains transfer data The data written to the SDR is converted to serial data and outp...

Page 333: ...ly becomes an output pin irrespective of the values in the port direction register bit1 of DDR3 and functions as the SO pin P30 UCK SCK pin The P30 UCK SCK pin functions as the general purpose I O port P30 It also functions as the shift clock I O pin SCK of the 8 bit serial I O or as the shift clock I O pin UCK of the UART When using the P30 UCK SCK pin as the shift clock input pin When using the ...

Page 334: ...de SPL 1 becomes high pull up state not Hi Z During the reset however pull up becomes invalid and the pin state becomes Hi Z DDR Pch Nch SCK PDR PUL P30 UCK SCK P32 UI SI SI P30 UCK SCK P31 UO SO P32 UI SI SPL 1 Internal data bus PDR read Resource output Stop mode SPL 1 Resource output enable Resource output available Pull up resistor PDR read At read modify write Output latch PDR write Pin PUL re...

Page 335: ...bit manipulation instruction make sure that the SST bit is 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0039H SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST 00000000B R W R W R W R W R W R W R W R W bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 003AH XXXXXXXXB R W R W R W R W R W R W R W R W R W Readable and Writable X SMR serial mode register Address Address Initial value Initial value SDR serial data register Unde...

Page 336: ...or prohibited Serial I O transfer is in progress Serial I O transfer is started or allowed Transfer direction selection bit LSB first serial I O transfer starts at the lowest bit MSB first serial I O transfer starts at the highest bit Shift clock selection bits SCK pin Internal shift clock External shift clock Output Output Output Input Serial data output allowance bit P31 UO SO is used as a gener...

Page 337: ...S1 and CKS0 bits to 11B For shift clock output SCKE bit 1 select an internal shift clock do not set the CKS1 and CKS0 bits to 11B Notes When shift clock output is allowed when this bit is 1 the P30 UCK SCK pin functions as the UCK SCK output pin irrespective of the general purpose port P30 state When using the P30 UCK SCK pin as a general purpose port P30 set its pin as the shift clock input pin s...

Page 338: ...nsfer terminated If this bit is set to 1 when the internal shift clock is selected when the CKS1 and CKS0 bits are not 11B the shift clock counter is cleared and serial I O transfer is started If this bit is set to 1 when the external shift clock is selected when the CKS1 and CKS0 bits are 11B serial I O transfer is allowed and the shift clock counter is cleared The transfer side enters the extern...

Page 339: ... bit serial data written to the SDR is transferred Transmission data does not remain in the SDR because it is shifted out via serial I O transfer At serial input operation The SDR functions as a reception data register When serial I O transfer is started SMR SST 1 the serially transferred reception data is stored in the SDR When the serial I O is in transfer operation When the serial I O is in tra...

Page 340: ...the interrupt request IRQC for CPU interrupt occurs Write 0 to the SIOF bit with the interrupt processing routine and clear the interrupt request When 8 bit serial output is completed the SIOF bit is set irrespective of the SIOE bit value If serial I O transfer stop SMR SST 0 and serial data transfer termination take place at the same time during serial I O operation the interrupt request flag bit...

Page 341: ...l data output pin SO Serial output operation via internal shift clock Serial output operation using the internal shift clock requires the settings shown in Figure 14 6 1 Figure 14 6 1 Settings Required for Serial Output Operation using Internal Shift Clock When serial output operation is started the contents of the SDR are output to the SO pin in synchronization with the falling edge of the select...

Page 342: ...it serial I O enters the idle state state in which it waits for the output of the next data set the external shift clock to a high level Figure 14 6 3 shows 8 bit serial output operation Figure 14 6 3 8 bit Serial Output Operation Operation at Serial Output Completion At the rising edge of the shift clock for serial data of the 8th bit the interrupt request flag bit SMR SIOF is set to 1 and the se...

Page 343: ... shift clock Serial input operation with the internal shift clock requires the settings shown in Figure 14 7 1 Figure 14 7 1 Settings Required for Serial Input Operation using Internal Shift Clock When serial input operation is started the value of the serial data input pin SI is captured and held in the SDR in synchronization with the rising edge of the selected internal shift clock In this case ...

Page 344: ...in which it is waiting for the output of the next data keep the external shift clock at a H level Figure 14 7 3 shows 8 bit serial input operation Figure 14 7 3 8 bit Serial Input Operation Operation at Serial Input Completion At the rising edge of the shift clock for the serial data of the 8th bit the interrupt request flag bit SMR SIOF is set to 1 and the serial I O start bit SMR SST is set clea...

Page 345: ...it serial I O continues data transfer without stopping the serial I O operation Figure 14 8 1 8 bit Serial I O Operation in Sleep Mode Internal Shift Clock 8 bit serial I O operation in stop mode In stop mode as shown in Figure 14 8 2 the 8 bit serial I O stops the serial I O operation and suspends data transfer After stop mode has been released reinitialize the 8 bit serial I O because operation ...

Page 346: ...fer destination must also be initialized If serial output is in operation set the SDR again before restarting the 8 bit serial I O Figure 14 8 3 8 bit Serial I O Operation at Issuance of Stop Request during Operation Internal Shift Clock 0 1 2 4 3 5 6 7 SCK output SST bit Oscillation stabilization wait time Stop mode request Clear via program SIOF bit Interrupt request SO pin output STP bit STBC r...

Page 347: ...ode has been released a transfer destination error occurs because operation is resumed halfway In this case initialize the 8 bit serial I O Figure 14 8 5 8 bit Serial I O Operation in Stop Mode External Shift Clock 0 1 2 4 3 7 5 6 SCK input SST bit SIOF bit Clock for the next data Transfer stop state Clear via program Interrupt request SO pin output STP bit STBC register Sleep mode Sleep mode rele...

Page 348: ...or this reason the transfer destination must also be initialized If serial output is in operation set the SDR again before restarting the 8 bit serial I O In this case when the external clock is input the SO pin output changes Figure 14 8 6 8 bit Serial I O Operation at Issuance of Stop Request during Operation External Shift Clock 0 1 2 4 3 5 0 1 7 6 SCK input SST bit Clock for the next data Oper...

Page 349: ...ternal shift clock input the highest bit level is output as the SO pin output level If LSB first is set the lowest bit level is output as the SO pin output level MSB first and LSB first are set when the external shift clock is input In this case however serial data output must be allowed SMR SOE 1 even if serial I O transfer is stopped SMR SST 0 If serial I O transfer stop SMR SST 0 and serial dat...

Page 350: ...tion between 8 bit serial I Os of MB89202 F202RA series for bidirectional serial I O operation When Bidirectional Serial I O Operation is Performed Figure 14 10 1 Example of 8 bit Serial I O Connection Interface between MB89202 F202RA Series SO SIO A SCK SI SIO B SCK SI SO Output Input Internal shift clock External shift clock ...

Page 351: ...B operation Set SI pin to serial data input input port Set SCK pin to shift clock input Set SO pin to serial data output Select external shift clock Select same data transfer shift direction as SIO A Allow serial data transfer Set output data Serial data transfer End of 8 bit transfer 3 Read input data The SST bit is the serial I O transfer start bit of the serial mode register SMR SST 1 2 3 If on...

Page 352: ... interrupt cycle 8 32 4 10 MHz 81 92 µs Coding example SMR EQU 0039H Address of serial mode register SDR EQU 003AH Address of serial data register SSEL EQU 003BH Address of serial UART selection register SIOF EQU SMR 7 Defines the interrupt request flag bit SST EQU SMR 0 Defines the serial I O transfer start bit ILR4 EQU 007EH Address of interrupt request setting register 4 INT_V DSEG ABS DATA SEG...

Page 353: ...usly The program uses the external shift clock to be input from the SCK pin Coding example DDR3 EQU 000DH Address of data direction register 3 SMR EQU 0039H Address of serial mode register SDR EQU 003AH Address of serial data register SSEL EQU 003BH Address of serial UART selection register SIOF EQU SMR 7 Defines the interrupt request flag bit SST EQU SMR 0 Defines the serial I O transfer start bi...

Page 354: ...selects the external shift clock and sets LSB first MOV SSEL 00000001B Selects the 8 bit serial I O SETB SST Allows serial I O transfer SETI Enables interrupts Interrupt processing routine WARI CLRB SIOF Clears the interrupt request flag PUSHW A XCHW A T PUSHW A MOV A SDR Reads transfer data SETB SST Allows serial I O transfer User processing POPW A XCHW A T POPW A RETI ENDS END ...

Page 355: ...chapter describes the functions and operation of the buzzer output 15 1 Overview of the Buzzer Output 15 2 Configuration of the Buzzer Output 15 3 Pin of the Buzzer Output 15 4 Buzzer Register BZCR 15 5 Program Example for Buzzer Output ...

Page 356: ...imer Note The time base timer supplies clock for the buzzer output Therefore buzzer output will be affected when time base timer is cleared Table 15 1 1 lists the four kinds of output frequencies square waves specifiable for the buzzer output Note Calculation example of an output frequency If time base timer output FCH 210 is selected in the buzzer register BZCR BZ2 1 BZ1 0 and BZ0 0 and the oscil...

Page 357: ...imer The buzzer register BZCR sets it Buzzer register BZCR The buzzer register BZCR is a register for setting the buzzer output frequency and enable the buzzer output When the BZCR register sets an output frequency other than 000B the buzzer output is enabled so that the P37 BZ PPG pin automatically becomes the buzzer output BZ pin Even if the PPG pin has been enabled the BZ pin has higher priorit...

Page 358: ...ardless of the value of output latch Even if the PPG output has been enabled it works as the BZ pin that has higher priority Block Diagram of the Pin Related to the Buzzer Output Figure 15 3 1 Block Diagram of Pin Related to Buzzer Output Note If pull up resistor supported is specified by the pull up setting register the state of the pin in stop mode SPL 1 is not Hi Z but H level pull up state Dur...

Page 359: ... 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0018H BZ2 BZ1 BZ0 000B R W R W R W R W FCH 1 1 1 1 1 1 1 1 1 1 1 1 Address Initial value Buzzer selection bits FCH 12 5 MHz Works as a general purpose output port P37 or the 12 bit PPG output PPG Outputs FCH 213 1 526 kHz to the BZ pin Outputs FCH 212 3 052 kHz to the BZ pin Outputs FCH 211 6 104 kHz to the BZ pin Outputs FCH 210 12 21 kHz to the BZ p...

Page 360: ...t If 000B is set to these bits the buzzer output is disabled and the pin works as a general purpose port P37 or as the 12 bit PPG output PPG With the exception of 000B the pin becomes the buzzer pin and outputs a square wave Even if the pin has been functioning as the 12 bit PPG output setting a value other than 000B causes the pin to work as the BZ pin prior to its operation as the PPG pin For th...

Page 361: ...Z pin and then the buzzer output is cut off If 212 FCH is selected when the oscillation FCH is 12 5 MHz the buzzer output frequency is calculated as follows Buzzer output frequency 12 5 MHz 212 12 5 MHz 4096 3 052 kHz Coding example BZCR EQU 0018H Address of the buzzer register Main program CSEG CODE SEGMENT MOV BZCR 00000010 Buzzer output on 3 052 kHz Oscillation of 12 5 MHz MOV BZCR 00000000 Buz...

Page 362: ...346 CHAPTER 15 BUZZER OUTPUT ...

Page 363: ...ter describes the functions and operation of the wild registers 16 1 Overview of the Wild Register Function 16 2 Configuration of the Wild Register Function 16 3 Registers of the Wild Register Function 16 4 Operations of the Wild Register Functions ...

Page 364: ...ddress with new data For example if an error exists in a program setting the address of the faulty part and correction data to the register can correct the faulty data Wild Register Applicable Addresses The address area where the wild register function can apply varies slightly with the models Table 16 1 1 shows the wild register applicable addresses for each model Note The wild register function ...

Page 365: ... address and data to be replaced by the wild register The MB89202 F202RA series incorporates two bytes for each register Control circuit part This part compares the data held in the address set registers and the actual data on the address bus If it detects a match it sets the data in the data setting register to the data bus The control circuit part can control the operation by the address compari...

Page 366: ...15 RA14 RA13 RA12 RA11 RA10 RA09 RA08 XXXXXXXX B 0043H R W R W R W R W R W R W R W R W WRARL0 WRARL1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0041H RA07 RA06 RA05 RA04 RA03 RA02 RA01 RA00 XXXXXXXX B 0044H R W R W R W R W R W R W R W R W WREN bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0046 H EN01 EN00 00 B R W R W WROR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0047H RESV1 RESV0 00B R W R W R W Readable a...

Page 367: ... bit5 bit4 bit3 bit2 bit1 bit0 WRDR0 0042H RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 XXXXXXXXB R W R W R W R W R W R W R W R W WRDR1 0045H RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 XXXXXXXXB R W R W R W R W R W R W R W R W R W Readable and Writable X Undefined Address Initial value Table 16 3 1 Functions of Data Setting Register WRDR Wild register number Register name Function 0 WRDR0 1 byte registers...

Page 368: ...it3 bit2 bit1 bit0 WRARH0 0040 H RA15 RA14 RA13 RA12 RA11 RA10 RA09 RA08 XXXXXXXX B R W R W R W R W R W R W R W R W WRARH1 0043 H RA15 RA14 RA13 RA12 RA11 RA10 RA09 RA08 XXXXXXXX B R W R W R W R W R W R W R W R W R W X Address Initial value Readable and Writable Undefined Table 16 3 2 Functions of Higher Address Set Register WRARH Wild register number Register name Function 0 WRARH0 1 byte registe...

Page 369: ...it3 bit2 bit1 bit0 WRARL0 0041H RA07 RA06 RA05 RA04 RA03 RA02 RA01 RA00 XXXXXXXXB R W R W R W R W R W R W R W R W WRARL1 0044H RA07 RA06 RA05 RA04 RA03 RA02 RA01 RA00 XXXXXXXX B R W R W R W R W R W R W R W R W R W X Address Initial value Readable and Writable Undefined Table 16 3 3 Functions of Lower Address Set Register WRARL Wild register number Register name Function 0 WRARL0 1 byte registers t...

Page 370: ...of Each Bit in Address Comparison EN Register WREN Bit name Function bit7 to bit2 Unused bits Undefined at read No effect to the operation at write bit1 EN01 When this bit is 0 the corresponding wild register function does not work When this bit is 1 the wild register function is enabled If there is a match with the address held in WRARH1 and WRARL1 the value of WRDR1 instead of ROM is output to t...

Page 371: ...355 CHAPTER 16 WILD REGISTER FUNCTION 16 3 5 Data Test Set Register WROR A test register Do not access this register ...

Page 372: ...mbers Table 16 4 1 Operation Order of Wild Register Operation Operation example 1 Set an address of the wild register correspondence area to the address set register Address FC36H data FFH WRARL0 36H WRARH0 FCH 2 Set the correction data to the data setting register WRDR0 B5H 3 Set 1 to the address comparison EN00 bit WREN 01H 4 The wild register works at the time of address matching When address F...

Page 373: ...ogrammer 3 Executing programs to write erase data This chapter explains Executing programs to write erase data Note A user must create a serial programmer for writing 17 1 Overview of Flash Memory 17 2 Flash Memory Control Status Register FMCS 17 3 Starting the Flash Memory Automatic Algorithm 17 4 Confirming the Automatic Algorithm Execution State 17 5 Detailed Explanation of Writing to Erasing F...

Page 374: ...dard commands Minimum of 10000 write erase operations MB89F202 F202RA High voltage supply on RST pin applicable to MB89F202RA only During writing data to or erasing all data in flash memory a typical 10V D C voltage should be applied at the RST pin After applying the high voltage wait for 10ms before writing data or erasing all data in flash memory And this applied voltage should be kept at the RS...

Page 375: ...e enable bit Disables data to be written into erased from flash memory Enables data to be written into erased from flash memory INTE 0 1 Causing an interrupt to the CPU to be generated bit Enables an interrupt when data writing erasing is completed Disables an interrupt when data writing erasing is completed Flash memory operation state indication bit Data is being written erased Data writing eras...

Page 376: ... 1 upon the termination of the flash memory automatic algorithm see Section 17 3 Starting the Flash Memory Automatic Algorithm The read modifier write RMW command always reads 1 from this bit bit5 WE Write enable bit Bit for write enabling flash memory areas When this bit is set to 1 a write instruction performed after a command sequence for a section from C000H to FFFFH see Section 17 3 Starting ...

Page 377: ...ta Address Data Read Reset 1 XXXX F0 4 FAAA AA F554 55 FAAA F0 RA RD Write program 4 FAAA AA F554 55 FAAA A0 PA PD Chip Erase 6 FAAA AA F554 55 FAAA 80 FAAA AA F554 55 FAAA 10 Both of the two types of Read Reset commands can reset the flash memory to read mode Notes The addresses shown in the table are those on the CPU memory map All addresses and data are represented in hexadecimal notation The l...

Page 378: ...Table 17 4 1 lists the bit assignments of the hardware sequence flags To determine whether automatic writing or chip sector erase is being executed the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control status register FMCS that indicates whether writing has been completed After writing erasing has terminated the state returns to the...

Page 379: ... address signal Automatic Erasing Read access during execution of the automatic erasing algorithm causes the flash memory to output 0 regardless of the value at the address specified by the address signal After the automatic erasing algorithm is executed 1 is output Note When the automatic algorithm comes to the end of its operation bit7 data polling changes its state asynchronously during a read ...

Page 380: ...ile the automatic writing erasing algorithm is being performed toggles flash memory and makes it output 1 and then 0 in turn regardless of the specified address Making successive read accesses when the automatic writing erasing algorithm ends makes flash memory to stop bit6 toggle and outputs the value of bit6 DATA 6 corresponding to the value read from the specified address The toggle bit becomes...

Page 381: ... Thus if this bit outputs 1 while the automatic algorithm is operating data writing or data erasing failed Bit5 indicates a failure when an attempt is made to write data into a non blank area without erasing any data In the case of such a failure fixed data cannot be read from bit7 data polling and bit6 toggle bit remains unchanged toggled If the time limit is exceeded while there is a failure 1 i...

Page 382: ...t output 1 and then 0 in turn regardless of the specified address Making successive read accesses while the automatic writing algorithm is being performed toggles flash memory and makes it output 1 regardless of the specified address Making successive read accesses when the automatic writing erasing algorithm ends makes flash memory to stop bit2 toggle and outputs the value of bit2 DATA 6 correspo...

Page 383: ...ce see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm for a write cycle to the bus to perform Read Reset Write Chip Erase operations Each bus write cycle must be performed continuously In addition whether the automatic algorithm has terminated can be determined using the data polling or other function At normal termination the flash memory is returned to the read reset ...

Page 384: ...of command sequences that execute the first and third bus operations However there are no essential differences between these command sequences The read reset state is the initial state of the flash memory When the power is turned on and when a command terminates normally the flash memory is set to the read reset state In the read reset state other commands wait for input In the read reset state d...

Page 385: ...xceeded flag DQ5 is determined to be an error Otherwise the data is viewed as if dummy data 1 had been written However when data is read in the read reset state the data remains 0 Data 0 can be set to data 1 only by erase operations All commands are ignored during execution of the automatic write algorithm If a hardware reset is started during writing the data of the written addresses will be unpr...

Page 386: ...efore start writing FMCS WE bit5 Enable flash memory write Write command sequence 1 FAAA AA 2 F554 55 3 FAAA A0 4 Write address Write data Read internal address Next address Data polling DQ7 Timing limit DQ5 Read internal address Data polling DQ7 Write error Final address NO YES FMCS WE bit5 Write disable flash memory Complete writing Confirm with the hardware sequence flags ...

Page 387: ... sequence table see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm continuously to the target sector in the flash memory The Chip Erase command is executed in six bus operations When writing of the sixth cycle is completed the chip erase operation is started For chip erase the user need not write to the flash memory before erasing During execution of the automatic erase...

Page 388: ...ernal reset or power on enables the flash security feature How to disable the Flash Security Feature Perform the chip erase operation Behavior under the Flash Security Feature Read operation invalid data read Write operation ignored Others For the configuration of the standard parallel programmer please follow the specification of parallel programmer In order to prevent the device form enabling th...

Page 389: ... reset does not initialize the flash memory and keeps the automatic algorithm operating Thus when the CPU starts a sequence after the reset is cancelled the flash memory may not have been in a read state Prevent a cause of a reset from occurring while the flash memory is writing or erasing Program Access to Flash Memory While the automatic algorithm is being activated any read access to the flash ...

Page 390: ...374 CHAPTER 17 FLASH MEMORY ...

Page 391: ...of the instructions mask options in MB89202 F202RA series and the pin states APPENDIX A I O Map APPENDIX B Overview of the Instructions APPENDIX C Mask Options APPENDIX D Programming EPROM with Evaluation Chip APPENDIX E Pin State of the MB89202 F202RA Series ...

Page 392: ...09H WDTC Watchdog control register R W 0 XXXX 000AH TBTC Time base timer control register R W 00 000 000BH Vacancy 000CH PDR3 Port 3 data register R W XXXXXXXX 000DH DDR3 Port 3 data direction register W 00000000 000EH RSFR Reset flag register R XXXX 000FH PDR4 Port 4 data register R W XXXX 0010H DDR4 Port 4 data direction register R W 0000 0011H OUT4 Port 4 output format register R W 0000 0012H P...

Page 393: ...IC1 External interrupt 1 control register 1 R W 00000000 0025H EIC2 External interrupt 1 control register 2 R W 0000 0026H Vacancy 0027H 0028H SMC Serial mode control register R W 00000 00 0029H SRC Serial rate control register R W 011000 002AH SSD Serial status and data register R W 00100 1X 002BH SIDR Serial input data register R XXXXXXXX SODR Serial output data register W XXXXXXXX 002CH UPC Clo...

Page 394: ...042H WRDR0 Data setting register 0 R W XXXXXXXX 0043H WRARH1 Higher address set register 1 R W XXXXXXXX 0044H WRARL1 Lower address set register 1 R W XXXXXXXX 0045H WRDR1 Data setting register 1 R W XXXXXXXX 0046H WREN Address comparison EN register R W 00 0047H WROR Wild register data test register R W 00 0048H to 005FH Vacancy 0060H PDR6 Port 6 data register R W XX 0061H DDR6 Port 6 data directi...

Page 395: ...00000 0071H PUL3 Port 3 pull up set register R W 00000000 0072H PUL5 Port 5 pull up set register R W 0 0073H to 0078H Prohibited area 0079H FMCS Flash memory control status register R W R 000X 007AH Prohibited area 007BH ILR1 Interrupt level set register 1 W 11111111 007CH ILR2 Interrupt level set register 2 W 11111111 007DH ILR3 Interrupt level set register 3 W 11111111 007EH ILR4 Interrupt level...

Page 396: ...re B 1 Correspondence between Instruction Codes and Instruction Map The instructions are classified into four groups including transfer instructions and branch instructions Various methods for addressing are supported Depending on the selection of an instruction and specification of operands 10 kinds of addressing can be selected Bit manipulation instructions are supported so read modify write ope...

Page 397: ...y accumulator 8 bits or 16 bits determined on basis of instruction to be used TH Higher 8 bits of the temporary accumulator 8 bits TL Lower 8 bits of the temporary accumulator 8 bits IX Index register 16 bits EP Extra pointer 16 bits PC Program counter 16 bits SP Stack pointer 16 bits PS Program status 16 bits dr Either accumulator or index register 16 bits CCR Condition code register 8 bits RP Re...

Page 398: ...automatic transfer from A to T when the instruction is executed The codes in this column indicate the following indicates no change dH indicates the higher 8 bits of the data coded for the operation AL and AH indicate the contents of AL and AH just before the execution of the instruction 00 indicates that it becomes 00 N Z V C Indicates whether the instruction changes the corresponding flags If is...

Page 399: ...g the area from 0000H to 00FFH In this addressing the higher one byte of the address is 00H Specify the lower one byte with the operand Figure B 1 1 shows an example Figure B 1 1 Example of Direct Addressing Extended Addressing The addressing which is indicated by ext in the instructions list is used for accessing the entire area of 64 KB In this addressing specify the higher one byte of the addre...

Page 400: ...in the instructions list is used for accessing the entire area of 64 KB In this addressing the contents of the first operand are signed and added to IX index register Then the results are used as the address Figure B 1 4 shows an example Figure B 1 4 Example of Index Addressing Pointer Addressing The addressing which is indicated by EP in the instructions list is used for accessing the entire area...

Page 401: ...In this addressing the operand directly becomes the immediate data The specification of byte word is determined using the operation code Figure B 1 7 shows an example Figure B 1 7 Example of Immediate Addressing Vector Addressing The addressing which is indicated by vct in the instructions list is used for branching to a subroutine registered in the table In this addressing the operation code incl...

Page 402: ...s an example Figure B 1 9 Example of Relative Addressing In this example the control jumps to the address holding the operation code of BNE causing an endless loop Inherent addressing This addressing which has no operand in the instructions list is used for performing an operation determined on the basis of the operation code In this addressing the operations differ depending on the instructions F...

Page 403: ...n executed in the main routine and a specific subroutine is to be called it is possible to verify that the contents of A are the predetermined value in the subroutine It is also possible to verify that the branch was not from an unexpected part so it is useful in judging that a runaway has occurred Figure B 2 2 shows an overview Figure B 2 2 MOVW A PC When this instruction is executed the contents...

Page 404: ... B 2 3 shows an overview Figure B 2 3 MULU A DIVU A This instruction divides T of 16 bits by AL of 8 bits without a sign stores the results in 8 bits to AL and stores the remainder of 8 bits to TL Both AH and TH become 0 For the operation the contents of AH before execution are not used If the results exceed 8 bits they are not guaranteed Also the fact that the results exceeded 8 bits is not indic...

Page 405: ...n the contents of A do not become the address holding the operation code of this instruction Instead they are the same as the address holding the next instruction In Figure B 2 5 therefore the value stored in A is 1235H agreeing with the address holding the operation code next to XCHW A PC Note that it is not 1234H but 1235H Figure B 2 6 shows an example of assembler coding Figure B 2 6 Usage Exam...

Page 406: ...ram size to be smaller Figure B 2 7 shows the overview Figure B 2 7 Executing Example of CALLV 3 When this instruction is executed the contents of the PC to be saved in the stack area are not the address holding the operation code of this instruction Instead they comprise the address holding the next instruction In Figure B 2 7 therefore the value saved in the stack 1232H and 1233H is the same as ...

Page 407: ...stination for read modify write is different from that for ordinary read I O port at bit manipulation For some I O ports the value of the I O pin is read at ordinary read meanwhile the value of output latch is read at bit manipulation This is to prevent the other bits of the output latch from being accidentally changed regardless of the I O direction and pin state Interrupt request flag bit at bit...

Page 408: ...7 5 MOV Ri A 3 1 Ri A 48 to 4F 6 MOV A d8 2 2 A d8 AL 04 7 MOV A dir 3 2 A dir AL 05 8 MOV A IX off 4 2 A IX off AL 06 9 MOV A ext 4 3 A ext AL 60 10 MOV A A 3 1 A A AL 92 11 MOV A EP 3 1 A EP AL 07 12 MOV A Ri 3 1 A Ri AL 08 to 0F 13 MOV dir d8 4 3 dir d8 85 14 MOV IX off d8 5 3 IX off d8 86 15 MOV EP d8 4 2 EP d8 87 16 MOV Ri d8 4 2 Ri d8 88 to 8F 17 MOVW dir A 4 2 dir AH dir 1 AL D5 18 MOVW IX ...

Page 409: ...SP A E1 33 MOVW A SP 2 1 A SP dH F1 34 MOV A T 3 1 A T 82 35 MOVW A T 4 1 A TH A 1 TL 83 36 MOVW IX d16 3 3 IX d16 E6 37 MOVW A PS 2 1 A PS dH 70 38 MOVW PS A 2 1 PS A 71 39 MOVW SP d16 3 3 SP d16 E5 40 SWAP 2 1 AH AL AL 10 41 SETB dir b 4 2 dir b 1 A8 to AF 42 CLRB dir b 4 2 dir b 0 A0 to A7 43 XCH A T 2 1 AL TL AL 42 44 XCHW A T 3 1 A T AL AH dH 43 45 XCHW A EP 3 1 A EP dH F7 46 XCHW A IX 3 1 A ...

Page 410: ... 2 A A dir C 25 4 ADDC A IX off 4 2 A A IX off C 26 5 ADDC A EP 3 1 A A EP C 27 6 ADDCW A 3 1 A A T C dH 23 7 ADDC A 2 1 AL AL TL C 22 8 SUBC A Ri 3 1 A A Ri C 38 to 3F 9 SUBC A d8 2 2 A A d8 C 34 10 SUBC A dir 3 2 A A dir C 35 11 SUBC A IX off 4 2 A A IX off C 36 12 SUBC A EP 3 1 A A EP C 37 13 SUBCW A 3 1 A T A C dH 33 14 SUBC A 2 1 AL TL AL C 32 15 INC Ri 4 1 Ri Ri 1 C8 to CF 16 INCW EP 3 1 EP ...

Page 411: ...P A EP 3 1 A EP 17 35 CMP A IX off 4 2 A IX off 16 36 CMP A Ri 3 1 A Ri 18 to 1F 37 DAA 2 1 decimal adjust for addition 84 38 DAS 2 1 decimal adjust for subtraction 94 39 XOR A 2 1 R 52 40 XOR A d8 2 2 R 54 41 XOR A dir 3 2 R 55 42 XOR A EP 3 1 R 57 Table B 4 2 List of Operation Instructions 2 4 No MNEMONIC Operation TL TH AH N Z V C OP CODE A A T A A T A A T C A C A A AL TL A AL d8 A AL dir A AL ...

Page 412: ... 50 AND A Ri 3 1 R 68 to 6F 51 OR A 2 1 R 72 52 OR A d8 2 2 R 74 53 OR A dir 3 2 R 75 54 OR A EP 3 1 R 77 55 OR A IX off 4 2 R 76 56 OR A Ri 3 1 R 78 to 7F 57 CMP dir d8 5 3 dir d8 95 Table B 4 2 List of Operation Instructions 3 4 No MNEMONIC Operation TL TH AH N Z V C OP CODE A AL IX off A AL Ri A AL TL A AL d8 A AL dir A AL EP A AL IX off A AL Ri A AL Ri A AL d8 A AL dir A AL EP A AL IX off A AL...

Page 413: ...if Z 0 then PC PC rel FC 3 BC BLO rel 3 2 if C 1 then PC PC rel F9 4 BNC BHS rel 3 2 if C 0 then PC PC rel F8 5 BN rel 3 2 if N 1 then PC PC rel FB 6 BP rel 3 2 if N 0 then PC PC rel FA 7 BLT rel 3 2 FF 8 BGE rel 3 2 FE 9 BBC dir b rel 5 3 if dir b 0 then PC PC rel B0 to B7 10 BBS dir b rel 5 3 if dir b 1 then PC PC rel B8 to BF 11 JMP A 2 1 PC A E0 12 JMP ext 3 3 PC ext 21 13 CALLV vct 6 1 vector...

Page 414: ...r Instructions No MNEMONIC Operation TL TH AH N Z V C OP CODE 1 PUSHW A 4 1 SP A SP SP 2 40 2 POPW A 4 1 A SP SP SP 2 dH 50 3 PUSHW IX 4 1 SP IX SP SP 2 41 4 POPW IX 4 1 IX SP SP SP 2 51 5 NOP 1 1 No operation 00 6 CLRC 1 1 C 0 R 81 7 SETC 1 1 C 1 S 91 8 CLRI 1 1 I 0 80 9 SETI 1 1 I 1 90 ...

Page 415: ...el A IX d IX d A IX d16 A IX MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC dir MOVW MOVW MOVW XCHW A EP A EP A EP A EP EP A A EP A EP A EP EP d8 EP d8 dir 7 dir 7 rel A EP EP A EP d16 A EP MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS dir INC DEC CALLV BNC A R0 A R0 A R0 A R0 R0 A A R0 A R0 A R0 R0 d8 R0 d8 dir 0 dir 0 rel R0 R0 0 rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS dir I...

Page 416: ...ettling time with FCH 12 5 MHz 01 214 FCH Approx 1 31 ms 10 217 FCH Approx 10 5 ms 11 218 FCH Approx 21 0 ms Selectable Fixed to 218 FCH Fixed to 218 FCH 2 Reset pin output With reset output Without reset output Selectable With reset output With reset output 3 Power on reset selection With power on reset Without power on reset Selectable With power on reset With power on reset FCH Main clock scill...

Page 417: ...f the Evaluation Chip Programming EPROM 1 Make the MBM27C256 equivalent setting for the EPROM programmer 2 Load the program data to the area from 0000H to 7FFFH of the EPROM programmer 3 Program the area from 0000H to 7FFFH with the EPROM programmer I O RAM 512bytes PROM 32Kbytes 0000H 0080H 0280H 8000H FFFFH PROM 32Kbytes 0000H 7FFFH In normal operation mode Corresponding address on the ROM progr...

Page 418: ...P37 BZ PPG Port I O or resource I O Hold Hold Hi Z 1 2 Hi Z P40 AN0 to P43 AN3 Port I O or resource I O Hold Hold Hi Z 2 Hi Z P50 PWM Port I O or resource I O Hold Hold Hi Z 2 Hi Z P60 P61 Port I O Hold Hold Hi Z 2 Hi Z P70 to P72 Port I O Hold Hold Hi Z 2 Hi Z 1 For port input and peripheral input the internal input level is fixed to prevent them from generating a leak via the input open However ...

Page 419: ...403 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...

Page 420: ...am for 8 16 bit Capture Timer Counter Pins 169 Block Diagram of 8 16 bit Capture Timer Counter 166 Notes on Using the 8 16 bit Capture Timer Counter 198 Pins of 8 16 bit Capture Timer Counter 168 Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts 184 Registers of 8 16 bit Capture Timer Counter 170 8 bit PWM Timer Block Diagram of an 8 bit PWM Timer 139 Block Diagram ...

Page 421: ...der the Flash Security Feature 372 Bidirectional Serial I O Operation When Bidirectional Serial I O Operation is Performed 334 Bit Manipulation Read Destination at Execution of a Bit Manipulation Instruction 391 Bits Bits for Controlling Acceptance of Interrupts 30 Bits for Indicating Arithmetic Operation Results 29 Block Diagram Block Diagram for 8 16 bit Capture Timer Counter Pins 169 Block Diag...

Page 422: ...cuit 1 Programming Example 241 Functions of External Interrupt Circuit 1 226 Functions of External Interrupt Circuit 2 Level Detection 244 I O Circuit Types 14 Interrupt during the Operation of External Interrupt Circuit 1 237 Interrupt during the Operation of External Interrupt Circuit 2 253 Operation of External Interrupt Circuit 1 239 Operation of External Interrupt Circuit 2 254 Pins Associate...

Page 423: ...de 68 DIP 32P M06 Package Dimension of DIP 32P M06 10 Pin Assignment of DIP 32P M06 8 E EIC External Interrupt Control Register 1 EIC1 232 External Interrupt Control Register 2 EIC2 235 EIE External Interrupt Circuit 2 Control Register EIE2 250 EIF External Interrupt 2 Flag Register EIF2 252 Erase Automatic Write Erase 364 365 366 Detailed Explanation of Flash Memory Write Erase 367 Erasing Automa...

Page 424: ... 8L 380 Features Features of MB89202 F202RA Series 2 Flash Content Protection Flash Content Protection 373 Flash Memory Detailed Explanation of Flash Memory Write Erase 367 Flash Memory Features 358 Program Access to Flash Memory 373 Writing to the Flash Memory 369 Writing to Erasing Flash Memory 358 Flash Memory Control Status Register Flash Memory Control Status Register FMCS 359 Flash Memory Re...

Page 425: ...Interrupt 8 16 bit Capture Timer Counter of Interrupts 183 Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins 248 Bits for Controlling Acceptance of Interrupts 30 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 230 Block Diagram of Circuitry Terminating at the Pins Associated with External I...

Page 426: ... Interval Timer Functions are Enabled 147 Interval Timer Function 116 162 Interval Timer Function Operation 185 Interval Timer Functions Functions to Output the Square Wave 136 Operations of Interval Timer Function Time base Timer 122 Operations of the Interval Timer Functions 148 Program Example of Interval Timer Function 200 Program Example of Interval Timer Functions 157 L Level Detection Funct...

Page 427: ...Operations for Selecting Memory Access Mode 72 Operations in Active Mode 59 Operations in Each Clock Mode 58 Operations in Standby Mode 63 Operations in the Standby Mode and at a Suspension 152 Operations of A D Conversion Functions 274 Operations of Clock Supply Function 122 Operations of Interval Timer Function Time base Timer 122 Operations of the 8 bit PWM Timer Functions 150 Operations of the...

Page 428: ...f Port 3 Registers 86 Operation of Port 3 88 Pins of Port 3 84 Registers PDR3 DDR3 and PUL3 of Port 3 85 Structure of Port 3 84 Port 4 Block Diagram of Port 4 91 Operation of Port 4 93 Pins of Port 4 90 Registers of Port 4 91 Structure of Port 4 90 Port 5 Block Diagram of Port 5 95 Functions of Port 5 Registers 96 Operation of Port 5 98 Pins of Port 5 94 Registers of Port 5 95 Structure of Port 5 ...

Page 429: ... PPG Control Register 4 RCR24 218 8 bit Serial I O Interrupt Register and Vector Table 324 A D Control Register 1 ADC1 266 A D Control Register 2 ADC2 268 A D Data Register ADDH and ADDL 270 A D Enable Register ADEN 271 Address Comparison EN Register WREN 354 Block Diagram of the Wild Register Function 349 Buzzer Register BZCR 343 Capture Control Register TCCR 171 Capture Data Registers H and L TC...

Page 430: ...r TCR0 173 Timer 0 Data Register TDR0 178 Timer 1 Control Register TCR1 175 Timer 1 Data Register TDR1 180 Timer Output Control Register TCR2 177 UART Interrupt Related Registers and Vector Table Addresses 303 UART relating Registers 289 Watchdog Control Register WDTC 130 Wild Register Addresses List 356 Wild Register Applicable Addresses 348 Wild Register Function 348 Register Bank Pointer Config...

Page 431: ... Rate Control Register SRC 292 SSD Serial Status and Data Register SSD 294 SSEL Serial Switch Register SSEL 301 Stabilization of Oscillation State of Reset Waiting for Stabilization of Oscillation 49 Stack 16 bit Data Storage State in Stack 26 Stack Area Stack Area for Interrupt Processing 42 Stack Operation Stack Operation at the Beginning of Interrupt Processing 41 Stack Operation at the End of ...

Page 432: ...Transferred Data Format 304 Transition Diagram for State Transition in Standby Mode 68 Transition to Standby Mode and Interrupt 70 Transmission Transmission Interrupt 303 Transmission Operations Transmission Operations in Operating Mode is 0 1 2 or 3 306 U UART Block Diagram of the UART relating Pins 288 Block Diagram of UART 284 Functions of UART 280 Program Example for UART 311 UART Relating Pin...

Page 433: ...egister Function 350 Wild Register Addresses List 356 Wild Register Applicable Addresses 348 Wild Register Function 348 WRARH Higher Address Set Register WRARH 352 WRARL Lower Address Set Register WRARL 353 WRDR Data Setting Register WRDR 351 WREN Address Comparison EN Register WREN 354 Write Automatic Write Erase 364 365 366 Detailed Explanation of Flash Memory Write Erase 367 Write 363 Writing N...

Page 434: ...418 INDEX ...

Page 435: ...U SEMICONDUCTOR CONTROLLER MANUAL F2MC 8L 8 BIT MICROCONTROLLER MB89202 F202RA Series HARDWARE MANUAL February 2008 the second edition Published FUJITSU LIMITED Electronic Devices Edited Strategic Business Development Dept ...

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