Fujitsu F2MC-8L F202RA, Hardware Manual

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CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
8.4.5 Timer 0 Data Register (TDR0)
The timer 0 data register (TDR0) is used to set the timer 0 value in the 8-bit mode of the
8/16-bit capture timer/counter or the interval timer value (interval timer function) or
counter value (counter function) of the lower 8 bits in 16-bit mode.
■
Timer 0 Data Register (TDR0)
The values set in this register are compared with those set in the counter. Figure 8.4-6 shows the bit
structure of timer 0 data register (TDR0).
Figure 8.4-6 Timer 0 Data Register (TDR0)
●
8-bit mode (timer 0)
The values set in this register are compared with those set in the counter. When the interval timer function
is used, an interval timer value is set. When the counter function is used, the count value to be detected is
set. When the count operation is allowed (TCR0: TSTR0 = 0
→
1), the value in TDR0 is set in (loaded to)
the comparator data latch and the counter is incremented.
When the values in the comparator data latch match those in the counter as a result of the increment, the
values in the TDR0 are reset in the comparator data latch, the counter is cleared, and the count operation is
continued.
The comparator data latch is reset when a match is detected, thus, the values written to the TDR0 when the
counter is in operation become valid from the next cycle (after match detection).
Note:
The values set in TDR0 when the interval timer is in operation can be calculated from the expression
shown below. However, the instruction cycle is affected by the clock mode and gear function.
Values set in TDR0 = interval time/(count clock cycle
×
instruction cycle) - 1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X : Undefined
Address
Initial value
001D
H
XXXXXXXX
B