Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Table 5-24
INSTRUMENT BUS REGISTER ADDRESSES
Right Bus
Register Circuit Board Write Read
Tune control data
Center Frequency Control 70 F0
Data steering Center Frequency Control 71
1st LO driver control
1 st LO Driver 72
1st LO phaselock control
Phaselock Control
73 F3
Front panel LEDs Front Panel 74
Front panel encoders
Front Panel F4
Span magnitude data
Span Attenuator
75
Span magnitude and
decade attenuator data
Span Attenuator
76
Control data
Preselector Driver 77
Option configuration
Preselector Driver F7
Post VR gain Log & Video Amplifier 78
Video display mode/gain Log & Video Amplifier 79
Digital storage data
Vertical Digital Storage 7 A FA
Digital storage control Vertical Digital Storage 7B
Video level/filter/blank Video Processor 7C
Left Bus
Sweep rate and mode
Sweep OF
Hoidoff, interrupt, trigger Sweep 1F
Crt readout data Crt Readout 2F
10 MHz IF gain and bw VR Motherboard #2 3F
Z-axis & RF deck control
Z-Axis/RF Interface 4F
Crt readout control Crt Readout 5F
When the 6800 reads from the instrument bus, it does
not configure the PIA to pulse DATA VALID as it does for a
write cycle. Rather the 6800 writes to control register B to
set CB2 low. CB2 low asserts DATA VALID, after the RC
delay allowing for the data to be accessed, and the 6800
then reads the data through peripheral interface B. After
reading the data, the 6800 writes again to control register B
to unassert DATA VALID.
Instrument Bus Poll
When the 6800 recognizes an interrupt request (SER
ftEQ asserted), it enters a service routine. As part of this
routine, it performs a parallel poll to find who is requesting
service. A parallel poll sequence is shown in Fig. 5-36.
The 6800 begins by writing an invalid address on the
instrument bus, FF; all address decoders on the bus ignore
this address. Next, the 6800 writes to control register A to
set CA2 high, asserting POLL. All boards that respond to a
poll recognize this line and contain logic that either responds
or prepares to respond when the 6800 causes DATA VALID
to be asserted. Each interrupt is assigned a data line as
shown in Table 5-25. The board originating that interrupt
pulls low on the corrsponding line.
5-86
REV AUG 1981