Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
The Controlled Oscillator operates between 25.032 and
25.094 MHz, depending on the drive from the Error Amplifi­
er. This signal is applied to the Offset Mixer, where it mixes
with the 25 MHz reference frequency. The difference fre­
quency, which is from 32 to 94 kHz, is applied to the
phase/frequency detector and compared to the -r N refer­
ence frequency. If the two signals are edge and frequency
coincident, phaselock occurs. If they do not coincide, an
error signal is generated, passed through the Error Amplifi­
er, and applied to the Controlled Oscillator. This forces the
oscillator to shift to the reference frequency. This evolution
typically lasts for only a few milliseconds, so the inner loop
phaselock is, for all practical purposes, instantaneous.
The outer loop, which includes the inner loop circuits
(Offset Mixer, Error Amplifier, and Controlled Oscillator),
consists of the Strobe Driver, Phase Gate, Error Amplifier,
and 1st LO. (The phaselock control circuits are a part of the
operation, but are not considered a part of the loop.)
The 25.032 to 25.094 MHz output from the Controlled
Oscillator is applied to the Strobe Driver, where it is divided
by five, filtered, and sent to the Phase Gate Detector as a
5.006 to 5.019 MHz strobe signal. This signal generates line
spectra that are equally spaced about 5 MHz apart over the
entire spectrum (at about the 400th line, which corresponds
to about 2 GHz). Assuming that the 1 st LO is tuned in that
vicinity, one of these lines is within 2.5 MHz of the 1 st LO
frequency. The Phase Gate outputs a signal that is propor­
tional to the difference between the 1 st LO frequency and
that of the nearest strobe line. The signal is counted by the
phaselock control circuits.
Now, as the search for phaselock begins, the
microcomputer moves the strobe in about 1 MHz incre­
ments. It does so by sending a new number for each step to
the
N Counter. With each change in the
η
- N output sig­
nal, the Controlled Oscillator frequency changes to match,
and the strobe signal shifts toward the 1st LO frequency.
When the Phase Gate generates an error that is below
500 kHz, it passes through the filter in the Error Amplifier
circuits, and the microcomputer is notified of the proximity
of the strobe. The microcomputer now backs the strobe
away from the 1 st LO frequency in smaller increments until
the 500 kHz bandwidth is encountered. This locates the 1 st
LO to be about 500 kHz away from the strobe signal. The
microcomputer now moves the strobe to the middle of the
bandwidth, about 250 kHz away, then takes three small
steps closer while noting the change in error frequency with
each step. With this information, the microcomputer can
compute the position of the 1st LO frequency, does so, and
places the strobe within approximately 10 kHz of the 1 st LO
frequency. Then, the microcomputer commands “ lock” ,
which puts a more precise servo system into operation, as
follows.
Previously, the microcomputer was moving the strobe
around to find coincidence with the 1 st LO frequency. The
F(s) amplifier in the Error Amplifier circuits will now change
the current to the FM Coil of the 1st LO so the 1st LO
frequency finds and locks on frequency with the strobe. Any
frequency difference between the strobe signal and the
1
st
LO will generate a correction voltage of low frequency that
is filtered by the F(s) amplifier, then used to drive the FM
Coil back to the strobe position. If the 1 st LO drifts beyond
the operating range of the F(s) amplifier, the microcomputer
is alerted and the remainder of the circuits indicate the direc­
tion of drift. The microcomputer then tunes the Center Fre­
quency Control circuits to null out any FM coil current in the
phaselock loop.
PHASELOCK CONTROL
Refer to the block diagram adjacent to Diagram 40.
The Phaselock Control section consists of the following
major circuits:
1
) the address decoder, which receives and decodes the
talk and listen commands for the phaselock loop;
2
) the service request circuits, which sense an impending
loss of phaselock, send a service request to the
microcomputer, and cancel the request when directed by
the microcomputer;
3) the data buffer, which transmits and buffers data from
the microcomputer to the phaselock control and inner loop
circuits;
4) the multiplexer divider circuits, which multiplex input sig­
nals, including the F ERROR signal, and divide the signal
frequency for application to the counter-buffer stages;
5) the counter buffer, which accumulates the divided signal
from the multiplexer-divider circuits; then, upon command
from the microcomputer, multiplexes the data from the buff­
ers to the data bus. Some status signals share one of these
buffer stages;
6
) the phaselock sensor circuit, which monitors the
SEARCH signal, and informs the microcomputer of
phaselock status.
Address Decoder
The addresses from the microcomputer are decoded by
decoder U7055. The phaselock control circuits have both a
talk address, where the counter-buffer circuits are instruct­
ed to talk on the data bus, and a listen address, where
U7041 is directed to receive data from the data bus. The
talk address is F3; the listen address is 73.
REV AUG 1981
5-71