Tektronix 492, 492P, Руководство по обслуживанию, Страница: 248 / 303

Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
VALID to strobe data into an addressed register during a
6800 write to the instrument bus. It is also asserted on 6800
reads to enable the data buffer. The RC delay following in­
verter U1013B provides data settling time on the bus before
DATA VALID goes high. U1013B’s open-collector output
pulls down faster than R1024 pulls up, so DATA VALID’s
low-high transition is delayed compared to its high-low
transition.
Peripheral In terfa ce A.
PAO—PA7 are configured as
outputs to drive the instrument bus address lines. The 6800
writes to this interface to address a register on the instru­
ment bus.
Both the A and B interface buffers are disabled if an ex­
ternal controller pulls the INTL CONT line low. They are also
disabled if P1020 is disconnected for diagnostic purposes.
Either releases the low on the output of U1037A. The inter­
rupt line buffer, U3043A, is also disabled. These buffers for
the address, data, and interrupt lines then decouple the
6800 from the instrument bus.
The MSB of the address determines the direction of data
through U3016, the data lines buffer. Instrument bus ad­
dresses 80 and above set U3016 to buffer data from the
instrument bus to the PIA (6800 read); address 7F and be­
low set U3016 to buffer data in the opposite direction (6800
write).
Peripheral In terface B.
ΡΒ0—PB7 are configured either
as inputs or outputs to transfer data from or to the instru­
ment bus. The 6800 writes data to this interface to send it to
a
register on the instrument bus and reads data from this
interface when it interrogates a register on the instrument
bus.
Pull-ups on the data lines result in all ones if a read cycle
inputs a byte when no instrument bus register is enabled.
The RC delay in the enable signal for buffer U3016 slows
the low-high transition at the input of the Schmitt trigger, but
has little effect on the high-low transition. This holds the
instrument bus data lines stable while DATA VALID is going
false, but has little effect when the data lines are to be driv­
en at the beginning of a write cycle.
Instrument Bus Registers
Instrument bus address lines are split into a right bus and
a left bus for economy in address decoding. On the right
bus, a board with an addressable register need only decode
ABO through AB3 and AB7; on the left bus, a board need
only decode AB4 through AB7. In both cases, AB7 indicates
read (high) or write (low), as it does for the instrument bus
interface data buffer noted above. The microcomputer com­
municates with the following registers to control assemblies
as shown in Table 5-24.
Instrument Bus Data Transfers
Data transfers on the instrument bus require two steps:
the 6800 writes the address to peripheral interface A and
then reads or writes the data through peripheral interface B.
When the 6800 writes to the instrument bus, it configures
the PIA to pulse DATA VALID (the CB2 output). The PIA
does this automatically after data is written to peripheral
interface B as shown in Fig. 5-35.
Table 5-23
PIA REGISTER AND INTERFACE SELECT CODES
RS1 RSO
Control R e g is te r Bit
CRA-2 CRB-2 R e g is te r o r I n te rfa c e
0
0 1
X Peripheral Interface A
0
0 0
X Data Direction Register A
0
1
X X Control Register A
1 0
X
1
Peripheral Interface B
1 0
X
0
Data Direction Register B
1 1
X
X Control Register B
REV AUG 1981
5-85