Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
transistor Q2056. The circuit includes potentiometer R2038
in the emitter circuit to allow for adjusting the post VR ampli
fier gain. The output is transformer coupled by T1059 to the
base of feedback amplifier transistor Q1048. This circuit in
cludes emitter degeneration through resistor R2042 and col-
lector-to-base feedback through resistor R1052. The
collector feedback is used in this instance to help provide a
well-defined output impedance of 50
Q.
Input impedance to
this stage is defined by transformer T1059 and resistor
R1058 across the primary.
This final VR amplifier stage is biased for relatively high
output current. This is required because the VR system is
sometimes driven at an increased output level of +10 dBm,
and more current is required to prevent gain compression. A
higher output level is required in low noise or low
intermodulation distortion operation to compensate for the
10 dB of gain that is switched out of the Log Amplifier.
From the final amplifier, the signal is applied through the
1.2 MHz bandpass filter that consists of capacitors C2033
and C2018 and the components between. This filter is a
double-tuned design and has an insertion loss of approxi
mately 2 dB.
As an aid to understanding the overall VR system func
tions, it is helpful to understand some aspects of filter de
sign. When designing a wide-bandpass filter, on the order of
ten percent or greater, stop-band attenuation becomes a
severe problem in two-pole filters. The result is that a given
filter design will degenerate into either a high-pass or a low-
pass filter. The design of the filter in the Post VR Amplifier
circuit degenerates into a low-pass unit. However, since the
VR system includes a bandpass filter at both the input and
the output, and since the input filter in the VR Input circuit
degenerates into a high-pass unit, the overall VR system
exhibits clean stop-band performance.
The output signal from the filter is applied through co
axial connector J682 to the Log Amplifier. The output level
is nominally at 0 dBm.
Digital Control Circuits
The Digital Control circuits provide address and data de
coding for the bandwidth and gain step selection and band
identification for the band leveling gain control, and provide
the control signals to the other sections of the VR system to
accomplish those tasks.
Address and data valid lines from the analyzer address
bus are applied to address decoder U4022 through connec
tor P1049 pins 9, 10, 12, 13, 14, and 20. Data bit 7 is also
applied through P1049 pin 7 as a supplemental address bit
to select between the latch that stores data for bandwidth
selection, and the latch that stores data for band identifica
tion and gain step selection.
Data lines from the analyzer data bus are applied through
connector P1049 pins 1, 2, 3, 4, 5, 6, and 8 to data latches
U3010'and U3017. Note that only data bits 0, 1, and 2 are
applied to latch U3010.
Latch U3010 stores the data that selects among the fil
ters in the 1st and 2nd Filter Select circuits. Outputs from
pins 2, 19, and 16 of U3010 are applied to the decimal de
coders in the filter select circuits through edge connector
pins G, F, and E to control the filter selection. Decoding is
done within the filter select circuits because it results in few
er lines between circuits and provides extra buffering to re
duce noise transmission between circuits.
Latch U3017 stores the data that select among the var
ious gain steps and that identify the selected frequency
band for control of the band leveling function. Outputs from
pins 2, 5, and 6 (corresponding to data bits 0, 1, and 2) are
applied to inverter transistors Q4035, Q3035, and Q4037,
respectively. From Q4035, the output signal is applied
through connector P1049 pin 32 to the 10 dB Gain Steps
circuit to control gain switching. From Q3035, the output
signal is applied through edge connector pin 25 to the 20 dB
Gain Steps circuit to control switching of the 10 dB gain
switch; from Q4037, the output signal is applied through
edge connector pin 27 to the 20 dB Gain Steps circuit to
control switching of the 20 dB gain step.
Outputs from latch U3017 pins 15, 16, 19, and 12 (corre
sponding to data bits 3, 4, 5, and 6) are applied to band
decoder U3023. an open collector decoder. If band 1 is se
lected, pin 1 output is low. These outputs are used in con
junction with a 7.5 volt reference source, provided by
operational amplifier U3038B and driver transistor Q3036,
to produce signals that are applied to a second operational
amplifier (U3038A). These signals correspond to the amount
of gain that must be supplied for each band to level the
output for all bands. The analog output from U3038A is ap
plied through edge connector pin BB to the gain control PIN
diode in the Band Leveling circuit. For example; if band 1
were selected (U3023 pin 1 low), the current path is through
potentiometer R2031 and the emitter of Q3036. From the
potentiometer arm, the voltage is applied through resistor
R2033 to the summing junction at the input to operational
amplifier U3038A, driving that junction more negative. This
shifts the output from U3038A more positive to increase the
current through band leveling PIN diode CR2021. Potenti
ometer R2031 provides for calibrating the current through
the PIN diode for band 1. In similar fashion, the other poten
tiometers (R3034, R3030, R3019, R3022, R3024, R3026,
R3032, R3029, and R3028) allow for adjusting the current
for each of the other bands.
5-28
REV FEB 1983
Содержание 492, 492P
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Страница 256: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up Fig 5 40 Frequency control encoder timing ...
Страница 263: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up Fig 5 43 9914 GPIA block diagram 5 100 REV AUG 1981 ...
Страница 299: ...Product 492 Ser 1 Date 2 12 85 Change Ref M55287 Fig 5 28 Basic tune voltage converter Page 2 of 6 ...