
Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
The voltage regulator part of the circuit is U2037A which
compares the +5 V REF and +5 V SENSE voltages, ampli
fies the difference, and applies the change to Q2023, the
driver transistor. The change is amplified by this stage and
applied to the base of series-pass transistor Q2024 chang
ing its conduction to correct for the original change to the
+5V.
The current regulator portion of the circuit is U2037B. A
change in current through R2017 is applied to the non-in
verting input of U2037B, which amplifies the change and
applies it to the base of the driver transistor Q2023. The
transistor amplifies the change which alters the bias of
Q2024, causing it to restore the current flow through R2017
to its former value.
The +15 V regulator is the same as the +5 V regulator,
except that the coupling circuits from the preamplifiers are
separated from one another. The — 15 V regulator is virtual
ly identical to the +5 V regulator. The - 5 V regulator dif
fers from the others in that a driver stage is not required, so
the preamplifiers drive the series-pass transistor (Q5013)
directly.
Over-voltage Protection Circuit
Zener diode VR1015 and SCR Q1010 form the over-volt
age protection circuit. If the +5 V supply passes
+ 6
V, the
potential on the gate of Q1010 biases it into conduction.
This forces the +5 V supply to ground; it remains at ground
potential until the analyzer is de-energized and turned on
again.
Fan Drive Circuit
The Fan Drive circuit provides a temperature-controlled
current drive to the fan motor. The circuit produces a three-
phase drive current of approximately 240 Hz operating fre
quency. The actual drive circuit operates as a ring counter.
Transistors Q1038 and Q1044 form a current regulator
that is controlled by thermistor RT2045, the value of which
varies inversely with the internal temperature of the analyz
er. The thermistor and a companion resistor R2042, fix the
voltage at the emitter of Q1044 at about —13 V at turn-on,
and more positive as the analyzer warms up.
The ring counter consists of three stages: Q1025 and
Q1020, with R1031/C1032 and R1027/C1018 as the fre
quency-determining components; Q2025 and Q1018, with
R1033/C1033 and R2019/C1019 as the frequency-deter
mining components; and Q2030 and Q2020 with
R2014/C2012 and R2016/C2018 as the frequency-deter
mining components. When the analyzer is energized, one of
5-98
the three ring counter stages begins conducting before the
others, owing to circuit imbalances. Assume that the upper
stage (Q1025 and Q1020) begins conducting before the oth
ers. The collector voltage of Q1025 is near -1 7 V which
fixes that point as the most negative in a ring consisting of
R1032, R1029, R1028, R2036, R2034, and R1036. Since
the emitter voltage of the three control transistors (Q1020,
Q1018, and Q2020) is the same, the voltage division around
the resistive ring is such that Q1018 and Q2020 remain cut
off. When the capacitive charge that holds Q1020 in con
duction bleeds off, the transistor cuts off and the next stage
can begin to conduct. The remaining two are in turn prevent
ed from operating until the RC combination discharges. The
fan motor inductance works in conjunction with the RC
components to regulate the switching of the stages.
This ring-counter action builds up slowly until the circuit
is producing a three-phase drive signal of about 240 Hz. The
inductance of the motor coils round off the otherwise sharp
corners of the driving signal, so the current waveform looks
a great deal like the output of a half-wave rectifier at P2020,
pins 1, 2, and 3. Each of the driving signals are approxi
mately
1 2 0
° apart, so as to drive the motor.
The rackmount/benchtop versions require an external
fan, B200. When this fan is connected, the internal fan
(B
1 0 0
) is disconnected.
492P GENERAL PURPOSE INTERFACE
BUS ^
The 492P, unlike the 492, includes GPIB capability pro
vided by two boards: the GPIB board and the GPIB Inter
face board. The GPIB board contains ROM and RAM used
by interface functions and the interface between the micro
computer and the GPIB. The GPIB Interface board holds the
GPIB buffers and address switches.
Address Decoding
RAM.
RAM on the GPIB board supplies I/O buffer space
for GPIB transfers. The RAM iCs, four bits wide, are paired
to make
8
-bit bytes at each address. For instance, U1032
and U1042 are both selected when HIRAM is asserted. The
1 0
lower bits on the address bus select an address cell with
in each IC. The RAM address range, 800 to 1000 (hex), is
decoded by half of U1028. Either RAM select line is enabled
by GPIBRAM from the Processor board and the state of
A
1 0
on the address bus.
GPIB Interface and Address Switch Register.
Either
the GPIB interface (U2047) or the address switch register
(U3039) is selected by the other half of U1028. The select
line for either is enabled by GPIA from the Processor board
REV AUG 1981
Содержание 492, 492P
Страница 12: ...492 492P Service Vol I SN B030000 up The 492 492P Spectrum Analyzer xii REV AUG 1981 ...
Страница 244: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up REV AUG 1981 5 81 ...
Страница 256: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up Fig 5 40 Frequency control encoder timing ...
Страница 263: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up Fig 5 43 9914 GPIA block diagram 5 100 REV AUG 1981 ...
Страница 299: ...Product 492 Ser 1 Date 2 12 85 Change Ref M55287 Fig 5 28 Basic tune voltage converter Page 2 of 6 ...