Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
tor C2037. Input and output impedances are matched with
broadband transformers T3026 and T3055. A 3 dB
attenuator, consisting of R2027, R2026, and R2028, is in
cluded at the filter input.
The 1 kHz resolution filter consists of a single two-pole
monolithic crystal filter, matched to the 50 Ω impedance with
broadband transformers T2035 and T2055. A 2 dB
attenuator, consisting of R2024, R2023, and R2025 is also
part of the filter.
The 100 Hz filter uses a pair of high Q crystals in a bal
anced two-pole ladder configuration. These crystals are
matched for both frequency and temperature characteris
tics. Input and output impedance matching is accomplished
primarily by transformers T1025 and T1039. Two small ca
pacitors in the same transformer circuit as the crystals
(C1030 and C1035) are adjustable to cancel the parallel ca
pacitance effect of the crystals. Also, a 2 dB attenuator is
included at the filter input and consists of resistors R1026,
R1028, and R1027.
10 dB Gain Step Circuit <18,
The 10 dB Gain circuit provides 10 dB of signal gain
when selected by the microcomputer. The circuit consists of
three stages of amplification, one stage provides variable
gain, the other two are fixed gain steps. The nominal input
signal level from the 1st Filter Select circuit is - 3 2 dBm for
a resolution bandwidth of 100 kHz. (All levels listed in this
description relate to the 100 kHz resolution.)
The output of Q2043 drives the input of the third amplifier
stage. This stage operates the same as the first stage ex
cept for gain variation. Feedback resistor R1060 is shunted
by PIN diode CR1053. As the current through the diode
increases, the resistance decreases and the gain of the
stage increases. Gain control of the stage is established by
the setting of the front panel AMPL CAL adjustment. Gain
range is about 14 dB.
Output impedance of the stage is 50 Ω, set by resistor
R1064. Nominal output level is —10 dBm for a full screen
display. This level may be as high as +0dBm when MIN
NOISE is active. 10 dB of gain is also removed from the Log
Amplifier to reduce the noise level and must be supplied by
the VR section.
20 dB Gain Steps Circuit
The 20 dB Gain Steps circuit provides —6dB, +4dB,
+ 14 dB, and +24 dB of gain in precise 10 dB steps. The
nominal —10 dBm input is supplied through pin P from the
10 dB Gain Steps circuit. This signal is applied to a chain of
three common-emitter amplifiers, each using emitter degen
eration. Changing the emitter resistance is used to change
amplifier gain under the direction of the microcomputer.
The nominal gain of the complete circuit is - 6 dB, with
Q2018, Q2042 and Q1062 biased off. This provides a nomi
nal — 16 dBm output. In this condition, control pins V and Y
are high, causing switching transistors Q2018, Q2042, and
Q1062 to be cut off.
The input signal is applied through an impedance trans
former, T3019, to the first amplifier stage consisting of a
differential pair (Q3016 and Q2027) and an emitter follower
output amplifier (Q1036). Negative feedback through R1031
and R2051, provide gain stabilization. An output resistor,
R2035, increases the output impedance of the composite
amplifier to approximately 50 Ω.
Gain of the input stage is fixed for all resolution
bandwidths except 30 Hz. (In instruments that may have the
30 Hz resolution bandwidth capability, the gain for 30 Hz will
be set to a precise level by activating Q2015. Transistor
Q2015 is biased on by a low on pin L. This adds R2025
(30 Hz level) across feedback resistor R2051. Adjustment
R2025 can now set the gain of the stage.)
The output from the 1 st stage is then applied to a com
mon emiter stage (Q2043). Gain of this stage, when transis
tor Q4039 is turned on, is 10 dB. When the base of Q4039
is pulled low by data bit 0 from Q4035 on the VR mother
board #1, the transistor saturates and shunts the emitter
load resistor R3048 with R3038 and the 10 dB Gain adjust
ment R3035.
When pin V is low, Q2018 and Q2042 are saturated, rais
ing the total gain of the first two amplifiers 20 dB. Variable
resistor R2023 is used to adjust the gain shift of the first
stage (Q1025) while the gain shift of the second stage
(Q1035) is fixed at +10 dB. This adjustment allows the gain
shift to be exactly set to +20 dB.
When pin Y is low, Q1062 is saturated, raising the gain of
the third amplifier (Q1043) by 10dB. Variable resistor
R1063 allows the gain shift to be exactly set to +10 dB.
Data bits 2, 1, and 0 control the gains of the 10 dB Gain
Steps circuit and the 20 dB Gain Steps circuit. Bit 2 controls
pin V, bit 1 controls pin Y, and bit 0 controls pin N. The data
is decoded and stored in latches on the VR mother board
#2. Table 5-5 shows the state of bits 2, 1, and 0 and the
gain shifts of amplifier stages Q2043, Q1025, Q1035, and
Q1043.
The output of the 20 dB Gain Steps circuit is attached to
coaxial connector J684. The signal is routed through a dou
ble coaxial cable to the Band Leveling circuit.
REV FEB 1983
5-25
Содержание 492, 492P
Страница 12: ...492 492P Service Vol I SN B030000 up The 492 492P Spectrum Analyzer xii REV AUG 1981 ...
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Страница 256: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up Fig 5 40 Frequency control encoder timing ...
Страница 263: ...Theory of Operation 492 492P Service Vol 1 SN B030000 up Fig 5 43 9914 GPIA block diagram 5 100 REV AUG 1981 ...
Страница 299: ...Product 492 Ser 1 Date 2 12 85 Change Ref M55287 Fig 5 28 Basic tune voltage converter Page 2 of 6 ...