Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
COLUMN 0-7
ROW
0 7
X X X X X X X X
X X X O O O O O
IDLE X X X O O O O O
POSITION X X X O O O O O
X X X O O O O O
X X X O O O O O
X X X O O O O O
X X X O O O O O
X = BLANK
O = DOT ON OR OFF
2 7 2 7 - 1 1 9
Fig. 5-19. C haracter scan.
generator (U1028), which generates the correct pattern of
blanking to draw the pattern of dots for the character.
The 8678 (U1028) character generator IC (Fig. 5-20) con­
tains a ROM with the correct pattern of 64 bits for each of
the 64 characters in its repetoire. The bit patterns are
accessed by a decoder that operates on the ASCII code on
the character generator inputs. The pattern of bits is
multiplexed one
8
-bit line at a time into a shift register that is
clocked out one bit at a time to control the crt Z-axis.
Character Generator Timing. The character generator
timing lines are called DOT, LINE, LE, and CLR. Each cycle
of DOT clocks one dot (bit) out of the shift register. A posi­
tive transition on LINE switches the next line (row) of dots
onto the shift register inputs; the dots are latched by a neg­
ative transition on LE (load enable), setting up the shift reg
ister to display another row of dots. CLR resets the line
counter to begin drawing another character.
DOT is ANDed from GEN ON, INC, and CRT CLK by
U1022B. Inversion by the gate restores the phase relation­
ship of the DOT input and the inverted clock used by the
rest of the character generator. LE is gated by U1022A
when the character counter reaches column 2. This loads
the shift register with the next row of dots, which is dis­
played starting at column 3. LINE advances the line (row)
counter after the scan of the current row begins to set up
the next row of dots on the shift register inputs; this occurs
at column count 4. CLR is asserted only once during the
scan of each character. It is decoded by U1014 when the
character counter reaches row
1
, column
0
, the first non­
blank row of dots scanned in each character.
See the character timing figure (Fig. 5-21) for the se­
quence of events to scan a character. At 1 on the figure, the
character generator finishes a character. When the counter
advances, decoder U1014 asserts ROW 0 COL 0, resetting
the GEN ON flip-flop on the next clock. This stops the
counter at row 0, column 1 (2 on the figure). When U2044
completes the time-out period and again sets the GEN ON
flip-flop, the character counter resumes the scan, first
causing LE (at 3) and LINE (at 4). Just before the scan en­
ters the actual character area (at
6
), CLR resets the charac­
ter generator line counter (at 5). The break (7 on the figure)
indicates that the scan continues. After the character is
scanned, the scan returns to the idle state;
8
and 9 corre­
spond to
1
and
2
on the timing figure.
Dot Delay. Each bit shifted out of the character gener­
ator is the value of a dot in the
8
x
8
matrix;
0
for a blank
and 1 for a dot that is to be written. As the scan progresses
at better than 3 MHz, a rather faint character display might
be expected. To brighten the dots that are written, a shift
register inserts some dot delay by stopping the counters
while holding the crt beam unblanked. The dot delay timing
is shown in Fig. 5-22.
A high on the character generator output (U1028-11)
sets the dot delay shift register (U1036A,B,D) input high
(assume Q of U1036C is high). It also sets the unblanking
flip-flop (U2036A) J input high; once set, the flip-flop
unblanks the beam during the rest of the dot delay cycle.
Because the shift register must have completed any pre­
vious dot delay before entering a new cycle, the character
generator high output also gates INC (increment) low at
U1022C (assuming the microcomputer has turned on the
readout). On the next clock, the highs on the two register
inputs are latched.
Meanwhile, INC low puts the character counters on hold
and disables the gate (U1022B) that clocks the character
generator U1036C, the INC flip-flop, stores the low on INC
at the next clock, putting a low on the dot delay shift regis­
ter input.
Successive clocks propagate the dot through the shift
register; when it emerges after three clocks, it is inverted by
U1018C to reset the unblanking flip-flop and gate INC high.
This sets U1036C again on the next clock. INC remains high
if the value of the next dot is
0
or is gated low to repeat the
dot delay cycle if the next dot is
1
.
5-50
REV AUG 1981