Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
4) it loads the latched numerator and denominator serially
into the divide circuit (subtractor in the block diagram) using
i
the contents of the 25-bit shift register as a mask;
5) it clears the denominator ripple counter (17-bit counter in
the block diagram) to zero.
Ten clock periods are required to load the numerator and
denominator into the divide circuit. The cycle starts on a
SYNC pulse and the first bit of the quotient is available
shortly after the first clock pulse following the next SYNC
pulse. Division is performed by repeated subtract and shift
operations. The quotient is arrived at serially with the most
significant bit first. Only
8
-bit accuracy is required, so, by
using the priority encoder output as a mask, the divider cir­
cuit is loaded with the
8
most significant bits of the denomi­
nator and the 16 most significant bits of the numerator.
(Ripple borrow for a 17 by 25-bit subtractor would be so
long as to be impractical.)
The peak circuit consists of a peak detector and an
8
-bit
peak shift register. In operation, the previous peak Y value
from the last set of samples is still stored in the peak shift
register at the start of a conversion cycle. At that time, the
peak detector, which is a serial compare circuit, is set to the
state that will question whether the old or new number is
larger. Each bit of the new value is then compared with the
corresponding bit of the old value, most significant bit first.
When one value is found to be larger, a flip-flop is set and
the smaller number is gated out of the shift register. The
start divide logic signal being true then forces the peak de­
tector to select the new value and ignore the number in the
shift register.
The peak/average selector, a multiplexer, selects either
the peak or average value to be routed to the memories
under control of the PEAK/'AVG signal. The selector output
is routed through the max hold circuit, which functions in the
same manner as the peak detector. When the MAX HOLD
signal is high, the value that is routed to the output multi­
plexer is the larger of two values: the current memory value
at the subject X coordinate or the previously selected peak
or average value.
Timing for setting up the divide operation and clearing
the numerator, denominator, and peak circuit is controlled
by a 10-stage Johnson counter. NOR-gate taps are taken
from appropriate stages to develop the necessary clear and
latch timing pulses. Because the denominator is loaded into
the divide circuit using a priority encoder, the most signifi­
cant bit is always a 1. Space and power were saved by
modifying the subtractor and not storing this
1
.
All data enter and leave the memory serially. Data read
from memory enter an
8
-bit shift register, and timed by
SYNC, are transferred to the vertical display output latch
(display register on the block diagram). The same shift regis­
ter is used for other purposes, so the DISPLAY ENABLE
signal prevents non-display information from being trans­
ferred to the output latches. An example of data moving
through this shift register is that during the B minus A dis­
play mode. The A value is first read from memory and
stored in the shift register. As the B value is read, the sub­
traction is done serially and the answer is applied to the shift
register. Since the subtraction must be performed least sig­
nificant bit first, a set of exclusive-0 R gates change the or­
der of extracting B from memory. The direction of shift for
the shift register is reversed also to present the most signifi­
cant bit to the proper display latch. The shift register output
is also applied to the output multiplexer.
In the subtraction, the operation performed by the serial
calculator is not merely B minus A. The actual expression
implemented is (B -A ) + K, where K is a serial input exter­
nal constant specified by the user. This permits zero to be
placed anywhere on the screen. To avoid confusion, when
(B -A ) + K results in an off-screen position, the subtractor
blanks the display. This is done by examining the carry bit
and borrow bit when the most significant bit is calculated. If
either bit is a
1
, the screen is blanked.
When SAVE A mode is not selected and both A and B
are being displayed, maximum resolution is obtained (1024
points across the display). If this display includes a very
narrow pulse, it is possible that the top of the pulse is only
as wide as a single X coordinate (2 to 2
17
samples). If this
maximum value were in the B table and SAVE A mode were
selected and B turned off, there would be an apparent drop
in amplitude. For this reason, when SAVE A mode is select­
ed, a special set of circuits in U1023 compares all A and B
values that have the same X value and stores the larger in
table A. This is accomplished by first reading the B value
and storing it in the display shift register. Then, as the A
value is read, it is compared with the B value and the larger
of the two is loaded into the display shift register. Finally, the
number in the shift register is written into memory from the
shift register. This operation is performed once each time
that SAVE A mode is selected.
Vertical control IC U1023 also contains a 3-bit synchro­
nous counter that identifies the specific bit of an
8
-bit verti­
cal value that is to be read from memory or written into
memory. This is the only memory addressing that is per­
formed by the vertical control IC. All other addressing is
under control of the horizontal control IC (U2032).
Digitizing Circuits. The input vertical signal, VID FLTR
OUT, coupled through edge connector pin 60 is applied
through buffer U2033 to sample and hold switch U1033,
which is controlled by flip-flop U1011B. Flip-flop U1011B
generates the sample pulse and is enabled during the clock
REV FEB 1983
5-41