Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 A
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Service Request Circuits
The service request circuits consist of multiplexer U6105,
one-shot U6028B, latch U6066A, and associated circuitry.
This circuitry alerts the microcomputer in the event that the
1 st LO has drifted too far.
The UP and DOWN signals from the window comparator
(located on the Error Amplifier board) drive NOR gate
U6015. Both signals are also sent to U4025, where their
status can be read by the microcomputer. When one of
these signals is high it indicates that the Error Amplifier is
approaching its operating limits and the microcomputer
should adjust the 1st LO frequency so the Error Amplifier
returns to the center of its range. A high at either input of
U6015B produces a negative transition that triggers one-
shot U6028B. U6028B remains set for about 35 *is and sets
U6066A, causing two actions to occur: The Q output drives
Q7060 into saturation initiating the service request for this
address and the complement output of U6066A pulls the 1G
and 2G inputs of multiplexer U6105 low, enabling both
sides. This device allows Q4090 and U6066A to respond to
inquiries by the microcomputer to determine which address
requested service. The microcomputer initiates the polling
routine, which consists of pulling the POLL signal and AB7
high, then interrogating each data bus line in succession to
determine which requested service; that is, which data line
is low. This is done by setting the 1Y output of U6105 high,
which causes Q4090 to pull the D2 line low. To affirm which
address requested service, the microcomputer now causes
the 7 address line to move low, which, via the 2Y line from
U6105, clocks U6066A to the reset state as the
microcomputer holds data bus line 2 low. This cancels the
service request by cutting off Q7060, permitting its output to
move high. In addition, the complement output of U6066A
moves high, disabling the inputs to U6105. This brings the
service request circuitry back to its original state.
Data Buffer
This consists of buffers U7041, U6078D, U6078A, and
U6078E. U7041 is the listen buffer for the Phaselock Con­
trol circuits. When address decoder U7055 is addressed to
listen by the microcomputer it enables U7041, which passes
on the buffered data to the other circuits in the Phaselock
Control and inner loop circuits. The function of each data
bits is as follows:
DO This line carries the data that preloads the
η
- N
counter in the synthesizer circuits bit by bit in serial
format.
D1 . The N LATCH signal is sent on this line. It is used
to latch the N DATA into the synthesizer counters.
D2 Reserved for future applications.
D3 This signal resets the buffer sequencer at the
outset of a talk cycle for the counters.
D4 This line (CONTROL LATCH) latches a control
word into the output buffers of U2025 on the Error
Amplifier board.
D5 This signal clears all the counter stages in the
counter-buffer circuits in anticipation of a count
sequence.
D
6
By controlling the state of U6066B, this line selects
the signal source to be passed through U2105 to
be counted.
D7 This line furnishes the clock pulses for two areas of
circuitry. First the clock, which starts out coincident
with the N DATA on line DO, is delayed by an RC
circuit; then, it passes through buffer U6078D
where it is sent in two directions. The signal is
buffered through U6078E and used as the clock
pulse for U6066B. Also the signal, now delayed, is
used as the shift register clock for the
- η
N counter
latches on the Synthesizer board. The slight delay
is to provide adequate setup time for the data prior
to the clock signal arriving.
Multiplexer-Divider
This circuit consists of U6078B, U2105, and U2091. The
F ERROR signal enters at pin 12 of the board where it is
routed through buffer U6078B and applied to multiplexer
U2105. This multiplexer selects between several signal
sources to be counted. However, all other possible signal
sources apply to future applications, so for the time being,
U2105 passes to only the F ERROR signal through to
U2091. The F ERROR signal enters the multiplexer at pin 4.
It is passed through to the 1Y output, and into the upper
section of dual four-bit binary counter U2091, where it is
divided by two, and sent out the QA output. This signal is
passed through the other side of the multiplexer, out the 2Y
line, into the lower section of U2091. The QC output of
U2091, which is the F ERROR signal divided by eight, is
applied to the first counter, U2065. The QD output, which is
F ERROR signal divided by 16, is used to control the
multiplexer, and to keep the microcomputer posted on the
progress of the count.
Refer to Fig. 5-29 which illustrates the timing relation­
ships. The circuit functions as follows. At the outset of a
count cycle, the microcomputer sets the D5 line high, to
clear all of the counters including U2091. All outputs of
U2091 that are connected are low. This enables U2105 to
pass signals. At the first negative edge from the F ERROR
5-72
REV AUG 1981