Tektronix 492, 492P, Руководство по обслуживанию, Страница: 8 / 303

492/492P Service Vol. I (SN B030000 & up)
LIST OF ILLUSTRATIONS (cont)
Fig. Page
No.
3-43 Response of the 100 kHz filter.................. 3-65
3-44 Calibration adjustments on the VR #1
module.......................................................
3-65
3-45 Typical response of 10 kHz, 100 kHz, and
1 MHz bandwidth filte rs ........................... 3-67
3-46 Test equipment setup for adjusting IF gain
and the location of the calibrator level
adjustment.................................................
3-68
3-47A Digital Storage adjustment
locations SN B043115 and above ..........
3-70
3-47 Digital Storage adjustments
SN B043114 and below .......................... 3-70
3-48 Location of binary switch (S1014) for
setting B —SAVE A reference level............
3-71
3-49 Band leveling adjustments and gain diodes
(when installed) on VR #2 module............ 3-72
3-50 Test equipment setup for calibrating band
leveling of the external mixer bands..........
3-73
3-51 Test equipment setup for calibrating
Preselector Driver..................................... 3-74
3-52 Preselector Driver adjustments and test
points.........................................................
3-74
3-53 Test equipment setupo for calibrating
Phaselock assembly................................. 3-76
3-54 Adjustments and test point locations in the
Phaselock module.....................................
3-77
4-1 Multipin (harmonica) connector
configuration............................................. 4-4
4-2 Color code for some tantalum capacitors. . 4-4
4-3 Diode polarity m arkings............................ 4-5
4-4 Electrode configuration for semiconductor
components...............................................
4-6
4-5 Preparing the VR module for service
showing how it is supported when on an
extender...................................................
4-9
4-6 RF deck of B040000 and up version
showing major asemblies.......................... 4-11
4-6A View of the 492/492P RF deck for
B039999 and below showing major
assemblies
and circuit boards.....................................
4-12
4-7 View of the 492/492P top deck showing
major assemblies....................................... 4-13
4-8 Removing YIG oscillator interface circuit
b o a rd ......................................................... 4-16
4-9 Fan Assembly ........................................... 4-18
4-10 Test equipment setup for adjusting return
loss for the 110 MHz IF assembly ............ 4-20
4-11 Location of the 110 MHz IF return loss
adjustments and IF Gain adjustment ........ 4-20
Fig. Page
N o .
4-12 LO section of 829 MHz converter showing
test points and connectors ........................ 4-22
4-13 Location of test jack and jumper on the
829 MHz amplifier b o a rd ........................... 4-23
4-14 Test equipment setup for aligning the
829 MHz filter ........................................... 4-24
4-15 Filter tune tabs in the 829 MHz converter . 4-25
4-16 Typical response when the first and
second resonators of the 829 MHz filter
are adjusted correctly ............................... 4-26
4-17 Typical response when the third and fourth
resonators are tuned correctly .................. 4-26
4-18 Test equipment setup for calibrating
the oscillator section of the
2182 MHz Phaselocked 2nd L O ................ 4-28
4-19 Adjustments and test point locations
within the oscillator section........................ 4-29
4-20 Construction of a coaxial test probe
for the 2182 MHz Phaselocked 2nd LO . . . 4-30
4-21 Test equipment setup for calibrating
the phaselocked section of the
2182 MHz Phaselocked 2nd L O ................ 4-31
4-22 Location of test points and components
associated with calibrating the
14-22 MHz Phaselock circuit .................... 4-32
4-23 Jumper positions between T1077
and T1075 versus frequency
compensation for the 14-22 MHz
Oscillator ................................................... 4-33
4-24 The Memory board option switch band
S1033 ....................................................... 4-36
4-25 A15 through A12 in microcomputer test
mode ......................................................... 4-38
4-26 A15 and Y0 through Y2 of address decoder
U2044 ....................................................... 4-38
4-27 Enable and Y0 through Y2 of address de­
coder U 1037B........................................... 4-39
4-28 A15 and Memory board address decoder
outputs ..................................................... 4-40
4-29 A15 and Y0 through Y2 of address decoder
U1021 on the GPIB board ........................ 4-41
4-30 One enable and outputs LORAM, HIRAM,
and GPS of address decoder U1028 on the
GPIB board ............................................... 4-41
4-31 Instrument bus check ............................... 4-41
5-1 Filter cross-section view ............................ 5-8
5-2 Filter equivalent circu it............................... 5-9
5-3 2182.0 MHz Cavity LO equivalent circuits . 5-13
5-4 Diplexer simplified schematic .................... 5-14
5-5 Amplifier signal path ................................. 5-15
5-6 Amplifier signal path ................................. 5-15
REV SEP 1983
vii