Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Table 5-11
SWEEP RATE SELECTION CODES
Sweep Rate D7 D
6
D5
D4
D3
2 0
με/div
1 1 0 1 1
50
1 0 1
1 1
1 0 0
1 0 0 1 1
2 0 0 0 1 0 1 1
500
0 0 1 1 1
1
ms/div
0 0 0 1 1
2 1 1 0 0
1
5
1 0 1 0 1
1 0 1 0 0 0
1
2 0
0 1 0 0 1
50
0 0 1 0
1
1 0 0 0 0 0
0 1
2 0 0 1 1 0 0 0
500
1 0 1 0 0
1
s/div
1 0 0 0 0
2 0 1 0 0 0
5
0 0
1 0 0
1 0 0 0 0 0 0
Manual
1 1 1 1 1
External
0 1 1 1 1
U2043 latches the data from port 1F. Line Q
6
, when
high, enables an interrupt to the microcomputer at the end
of a sweep. This is done as follows: At rest, U2024A is reset
and the low at its Q output holds U2024B in the set state.
When the sweep ends (which constitutes an interrupt
event), the positive edge out of inverter U1052A clocks
U2024A to the set condition and the Q output of U2024A,
through inverter U3061A causes Q4052 to conduct, forcing
SER REQ low. The microcomputer responds by setting the
interrupt read line low; that is, it polls all addresses serially,
which eventually places a high at AB7 and POLL simulta­
neously (Fig. 5-24). This causes a high at the output of
U4016D (the Q of U2024A is low, since the flip-flop is now
set), and saturates Q4051, pulling the D4 line low (this iden­
tifies the sweep board as the service request originator).
Now, the microcomputer clocks an interrupt clear pulse to
reset U2024B. This in turn, resets U2024B which sets
U2024A. The circuit has returned to its reset stage.
U5052A and U5052B produce the interrupt read and
clear signals. When the microcomputer wants to read or
clear, it sets the POLL line high. Address bus line AB7 is
high to read, resulting in a low at the output of U5052A. AB7
is low to clear, which results in a high at the output of
U5052B.
SPAN ATTENUATOR < ^>
The Span Attenuator, under control of the micro­
computer, selects the appropriate attenuation factor for the
incoming sweep signal, to establish the frequency span. Re­
fer to the block diagram adjacent to Diagram 35. The Span
Attenuator consists of digital control circuits, which receive
and decode the address and instructions from the
microcomputer; the input amplifiers, which perform noise re­
duction and signal inversion on the incoming sweep signal;
the digital-to-analog converter, which attenuates the sweep
signal to the desired amplitude for driving the 1 st LO Driver
and Preselector Driver circuits; and the decade attenuator,
which provides three decades of attenuation for the output
signals.
Digital Control
Decoder U5025 decodes the address information from
the address bus and sends a low signal to either of the two
latches, U1025 (address 75) or U2015 (address 76), when a
latch is addressed and the DATA VALID line moves high.
(The data is stored in the latches on the trailing edge of the
DATA VALID signal.) Logic buffer U4015 reduces loading of
the data bus. Latch U1025 stores data that controls the
eight least significant digits of the span attenuation factor.
Latch U2015 stores data that controls the two most signifi­
cant digits of the span attenuation factor, and other func­
tions on the board. When a span attenuation factor is
selected, the microcomputer selects an address and places
the first byte of the data on the bus. The DATA VALID sig­
nal causes the data to be stored in one of the two latches.
Then the second address is called and the next byte is
stored in the other latch. The block diagram illustrates the
significance of each bit in tables near the affected circuit. A
logic
1
represents the more positive of two levels or high
state, and a logic
0
represents the more negative of two
levels or low state.
Input Section
The sweep signal and its ground reference are applied to
differential input buffer U3036. Any signals or noise induced
in the two signal transmission paths are cancelled by this
stage.
The following stage consists of amplifier U3032, plus
switching transistors Q2025, Q2028, and Q2023. Different
mixing modes require the 2nd LO frequency to either in-
5-58
REV AUG 1981