Tektronix 492, 492P, Руководство по обслуживанию, Страница: 206 / 303

Theory of Operation
— 492 /4 9 2 P
Service Vol. 1 (SN
B 030000 &
up)
A block diagram of the Horizontal control IC U2032 is
illustrated in Fig. 5-16. The horizontal analog voltage is con­
verted to a current table value through the use of a
1 0
-bit
tracking analog-to-digital converter, which consists of an
up/down interlock and 10-bit up/down counter (U2032) and
an external 10-bit digital-to-analog converter (U2036). As
the sweep moves to the right, the counter increments; as
the sweep retraces, the counter decrements. Each time the
counter increments, a new X coordinate value is generated
(the digital-to-analog converter output) and a ST DIV (start
divide) signal is generated to start the storage cycle. The
increment clock is the SYNC signal, the decrement clock is
the basic 1 MHz clock divided by two. When SAVE A mode
is selected, the counter skips every other binary number.
Thus, only B coordinates appear as addresses.
Horizontal Section ^25,
Intelligence for the horizontal system is provided by a
programmable logic array ROM state device (PLA). This
PLA determines which trace is to be written on the screen,
determines when to switch from read to write, generates the
B -A coordination signals for vertical control IC U1023,
controls the incrementing of the 9-bit display counter, and
processes requests for the memory bus. Of these, the only
function not obvious is the memory bus request. When an
external device elects to read from or write to memory, it
must request permission by allowing the BUS REQ (bus
request) signal to go high. When that time becomes avail­
able, the PLA pulls the BUS REQ line low, signalling the
start of a request cycle. For the next eight clock cycles, the
multiplexer output lines are driven to the high impedance
tristate mode.
Address Registers and Buffers. Address counting is
accomplished by registers U2022, U2016, and U2012.
These count INCR ADRS (increment address) pulses after
having been reset to zero by the CONT W (control write)
signal from the vertical section. From the address register,
the outputs are applied to tristate buffers U
1 0 2 2
and
U
1 0 1
-
6
, which buffer the
1 0
-bits of address from the
counters and the DS R/W (digital storage read/write) signal
line from the vertical section interface logic and multiplex
those signals onto the HD (horizontal display) lines and R/W
(read/write) line to the memories. These buffers are enabled
only during the bus grant portion of the cycle for display of
memory data. At all other times, horizontal control IC U2032
outputs control the HD lines to determine the memory ad­
dress for update of memory data.
Tracking Analog-to-Digital Converter. As discussed
previously, the
1 0
-bit digital-to-analog converter operates as
part of the loop that derives a binary equivalent of the SWP
(sweep) input signal from the Sweep board. Converter
U2036 accepts the output from the U2032 10-bit up/down
counter and converts that output to an analog current that
is subtracted from the sweep signal, which is applied at the
edge connector pin 60 and through buffer U2044B. The re­
sult of this subtraction is then supplied to up comparator
U2038A and down comparator U2038B, to produce the UP
or DOWN signal, as appropriate to control the direction of
the count of the 10-bit up/down counter in U2032. The
counter then counts in the appropriate direction, thereby
changing the digital-to-analog converter output to reflect the
proper value. Overflow detector U1032 and underflow de­
tector U1034 prevent the counter from counting too high or
too low.
The combination of the up/down interlock, 10-bit
up/down register, 9-bit display counter, and horizontal dis­
play multiplexer constitute the primary circuits that:
1) convert the sweep voltage to binary form to generate X
values to be written into memory, or
2) read the X values from memory by counting sync cycles
and causing the external logic to read stored data from
memory and produce a vertical signal (Y value) for each
corresponding X value.
During acquisition cycles, the 10-bit up/down counter,
controlled by the up/down interlock, operates in a loop with
the external
1 0
-bit digital-to-analog converter to derive the
equivalent (X value) of a sample section of the sweep volt­
age. From the counter, the 10-bit output is applied to the 10-
bit up/down register. During display cycles, the 9-bit display
counter counts sync pulses to derive the X value. Either the
1 0
-bit up/down register output or the display register output
is applied to the horizontal multiplexer under control of the
SELECT signal from the PLA. From the multiplexer, the out­
put is applied to the memories.
Update Marker Circuits. From U2032, the HD (horizon­
tal display) signals are also applied to 10-bit latches U1024
and U1018. The outputs of these latches are applied to 10-
bit digital-to-analog converter U2034. From the converter,
the output current is applied through buffer U2044A, where
it is converted to a voltage, to comparator U2042, which
compares it with the sweep voltage and applies the output
voltage to digital one-shot U1014A. The period of this one-
shot is determined by counter U2024 under control of the
low DISP ENBL (display enable) signal from the PLA in the
horizontal control IC U2032. DISP ENBL, when high, indi­
cates that valid data are to be transferred. Conversely,
when DISP ENBL is low, the lack of valid data indicates
retrace. One-shot U1014A produces the INTENSITY signal
that is used to temporarily prevent counting by the 9-bit
display counter in U2032, thereby effectively stopping the
beam for a short time and causing a bright spot on the
marker trace (cursor) to indicate the X point being updated.
Also note that buffer U2044A also produces the HORIZ SIG
(horizontal signal) that is sent to the Deflection Amplifiers.
Fast Retrace Blanking. Between the display of the B
memory contents and display of the A memory contents, a
REV FEB 1983
5-43