Tektronix 492, 492P, Руководство по обслуживанию

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Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
Phaselock Control, and 25 MHz plus a - ^ N frequency, de­
termined by the -
h
N number, for the Offset Mixer. The N
number produced by the Synthesizer, is determined by the
microcomputer and ranges from 32 to 94 kHz.
The Error Amplifier:
1) integrates the error signals from the Offset Mixer and
produces a correction voltage to pull the Control Oscillator
to a frequency that is synchronous with the
N signal;
2) generates a STROBE ENABLE to enable the strobe gen­
erator in the Strobe Driver circuit;
3) produces an UP or DOWN signal to alert the
microcomputer that the drive current to the 1 st LO FM coil
is reaching its limit in holding the 1st LO in phaselock;
4) generates an F ERROR signal, from the outer loop ER­
ROR 1 signal, to be used by the Phaselock Control in deter­
mining the proximity of the 1st LO frequency to the strobe
line.
Synthesizer Circuits
The Synthesizer can be divided into the following func­
tional blocks: the 100 MHz divider, the 50 MHz divider, and
the -
5
- N counter.
100 MHz Divider. This circuit consists of flip-flop U3030,
and differential pair Q3040 and Q3041. The 100 MHz signal
from the 3rd Converter stage is applied to the clock input of
U3030. (One-half of U3030 is used to furnish a stable bias
source for the clock input.) The signal from the Q output is
applied to Q3041, from which it is sent to the Phaselock
Control circuits. The signal from the complement output of
U3030 is applied through Q3040 to U1040B, the 50 MHz
divider.
50 MHz Divider. This circuit consists of U1040B. The
50 MHz from the collector of Q3040 is applied to the clock
input of flip-flop U1040B which divides the signal to 25 MHz.
The signal from the Q output is sent to the Offset Mixer
circuits. The complement signal is applied to the -τ- N
Counter.
-s- N Counter. This stage consists of two shift
register/latches U2020 and U2030; three counters, U2010,
U1020, and U1030; and flip-flop U1040A. The circuit is con­
trolled by three signals from the microcomputer by way of
the Phaselock Control circuits. The -=- N Counter is used to
furnish the 32 to 94 kHz reference frequency, which is ap­
plied to the Offset Mixer circuits. When power is first ap­
plied, and before phaselock is selected, this counter
typically operates at about
6
kHz.
5-74
When phaselock operation is selected, the micro­
computer sends data and a data clock to load a number into
the latches, which accept and store serial data. The num­
bers that come from the microcomputer range from about
3300 to 3830, so the count remaining, until the counters
overflow, is from about 265 to 795. When the number is
loaded, the N LATCH signal transfers the number from the
input shift registers to the output registers of U2020 and
U2030 where they are available to the counter stages. This
presets the counters to a predetermined value, as just men­
tioned. Once loaded, the counters count at a 25 MHz rate to
accumulate the remaining number of digits until they are full.
Then the TC output of U1030 moves high and U1040A
changes state. This presets the N number in the counter
stages for another count cycle. The TC output of U1030 is
again simultaneously set low so the next cycle of the
25 MHz clocks U1040A back to the reset condition. The
resultant output of U1040A is a series of positive pulses
that range in period from 10 ^s to 31 which is equivalent
to 94 to 32 kHz. This signal is sent to the Offset Mixer for
comparison with the difference frequency generated in the
mixer circuit.
Error Amplifier
The Error Amplifier circuits consist of the digital control
circuits, which decode the data from the microcomputer to
drive other circuits on the board; the inner loop error voltage
amplifier, which furnishes the tune voltage to the Controlled
Oscillator; the search amplifier which drives the phaselock
sensor circuits on the Phaselock Control board and the FM
coil of the 1st LO; the window comparator which drives the
service request circuits on the Phaselock Control board;
and the error signal filter which filters and squares the ER­
ROR 1 signal from the Phase Gate, and applies it to the
multiplexer-divider circuits on the Phaselock Control board.
Digital Control Circuits. These consist of shift register
U2025 and quad switch U2037. Data from the micro­
computer is fed serially, by way of the Phaselock Control
circuits into the shift register, then transferred to the output
lines by the LATCH signal. Table 5-19 lists the purpose of
the output lines.
Error Voltage Amplifier. This stage, which consists of
differential amplifier U3075 (shown on Diagram 41) and sur­
rounding components, compares the outputs of the
phase/frequency detector on the Offset Mixer board, fur­
nishing an oscillator tune voltage to the Controlled Oscilla­
tor. Refer to the Offset Mixer description that follows for a
more detailed description of this circuit.
REV AUG 1981