Tektronix 492, 492P, Руководство по обслуживанию, Страница: 262 / 303

Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
and chosen by A3. When A3 equals 0, it selects the GPIB
interface; when A3 equals 1, it selects the switch register.
The GPIB interface is described below. The address switch
register is a buffer, U3039, for the rear-panel GPIB AD­
DRESS, LF OR EOI, TALK ONLY, and LISTEN ONLY
switches.
ROM. ROM on the GPIB board contains the portion of
the instrument operating system that handles GPIB data
transfers. This portion of the firmware decodes and re­
sponds to messages received on the bus, transferring con­
trol to the appropriate subroutines in Memory board
firmware to execute the actions called for by the message.
The ROM address space is divided into two banks, either
of which can be filled with four
2
k packages or a single
8
k
package. Straps on the board are set to control decoder
U1021 and to route signals as needed to match the ICs that
are installed. For 2k ROMs, U1021 decodes A11 through
A13 to assert one of its eight chip-enable outputs during a
read cycle within the ROM address range (4000—8000, i.e.,
A14 high and A15 low). For
8
k ROMs, U1021 decodes only
A13 to assert either its Y0 or Y4 output. Straps on U2012
and U3012 inputs are set to apply the correct enable and
address signals for either kind of ROM.
GPIB Interface
The GPIB interface is based on the 9914 general purpose
interface adapter (GPIA). U2047, the GPIA, performs the
majority of the functions specified in IEEE Standard 488-
1978 and allows firmware implementation of the rest of
those functions. These functions are not explained here, but
are discussed in some detail in an appendix in the 492P
Programmer’s manual.
The GPIA’s internal logic handles:
Source and acceptor handshakes
Talker and listener functions
Recognizing GPIB address
Service request (SRQ)
Remote/local function
Local lockout
Serial and parallel poll response
Respond to device clear
Respond to device trigger
NRFD hoidoff when receiving data
GPIA Block Diagram
The bus and register organization of the GPIA is shown
in Fig. 5-43. The 13 registers are the vehicles used for com­
munication between the 492P microcomputer and the GPIB.
Some registers provide a link between the microcomputer
and GPIB; others are used by the microcomputer to control
the GPIA and obtain status information.
The registers are addressed by signal lines RS0 through
RS2 and the DBIN input (connected to the microcomputer
read/write line): DBIN high selects read registers, DBIN low
selects write registers. The registers are shown in Table
5-25.
Two interrupt status registers keep track of changes that
may require microcomputer attention: data byte received or
sent, EOI, GET, DCL, or IFC received, a remote/local state
change has occurred, and ATN going false are examples.
Corresponding interrupt mask registers are set by the
microcomputer to control interrupt status results in an
interrupt.
The address status register indicates the remote/local
state of the GPIA, the state of ATN, and the listener/talker
addressed states. The bus status register reflects the cur­
rent state of GPIB bus management lines.
The auxiliary command register receives commands that
control chip functions and local messages to the GPIA func­
tions (such as rtl—return to local).
The address register contains the instrument’s primary
address.
The serial poll register contains the status byte.
The command pass-through register connects the GPIB
data lines to the microcomputer data lines to transfer com­
mands not automatically handled by the GPIA.
The parallel poll register is used by the microcomputer to
respond to a parallel poll.
The data-in and data-out registers are the route for data
transferred between the microcomputer bus and the GPIB
when the instrument is either addressed as a listener or
talker. The 9914 automatically asserts NRFD until the
microcomputer reads the data-in register.
GPIB Buffers. Two transceivers on the GPIB Interface
board buffer signals on the GPIB.
The data bus buffers, in U1012, are controlled by two
signals: TE (talk enable) and PE (pull-up enable). TE from
the GPIA sets the direction of data flow: high means GPIA
to GPIB and low GPIB to GPIA. PE low disables the driver
pull-ups for open collector operation when ATN is asserted;
this disables tri-state operation, which is required during a
parallel poll (when ATN is asserted).
REV AUG 1981
5-99