Sun Microsystems Netra X4200 M2, Руководство по обслуживанию

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128 Netra X4200 M2 Server Service Manual • May 2007
78 Initializes IPL devices controlled by BIOS and option ROMs.
7A Initializes remaining option ROMs.
7C Generate and write contents of ESCD in NVRAM.
84 Log errors encountered during POST.
85 Display errors to the user and gets the user response for error.
87 Execute BIOS setup if needed/requested.
8C After all device initialization is done, programmed any user selectable parameters relating
to NB/SB, such as timing parameters, non-cacheable regions and the shadow RAM
cacheability, and do any other NB/SB/PCIX/OEM specific programming needed during
Late-POST. Background scrubbing for DRAM, and L1 and L2 caches are set up based on
setup questions. Get the DRAM scrub limits from each node. Workaround for erratum
#101 applied here.
8D Build ACPI tables (if ACPI is supported).
8E Program the peripheral parameters. Enable/Disable NMI as selected.
90 Late POST initialization of system management interrupt.
A0 Check boot password if installed.
A1 Clean-up work needed before booting to OS.
A2 Takes care of runtime image preparation for different BIOS modules. Fill the free area in
F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the
runtime language module. Disables the system configuration display if needed.
A4 Initialize runtime language module.
A7 Displays the system configuration screen if enabled. Initialize the CPUs before boot, which
includes the programming of the MTRRs.
A8 Prepare CPU for OS boot including final MTRR values.
A9 Wait for user input at config display if needed.
AA Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB Prepare BBS for Int 19 boot.
AC Any kind of Chipsets (NB/SB) specific programming needed during End- POST, just
before giving control to runtime code booting to OS. Programmed the system BIOS
(0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming
needed during End-POST. Copy OEM specific data from POST_DSEG to RUN_CSEG.
TABLE B-2
POST Code Checkpoints (Continued)
Post Code Description