
ML62Q1000 Series User's Manual
Chapter 13 I2C Master
FEUL62Q1000
13-20
Table 13-5 Relationship between Communication Speeds and HSCLK Clock Counts (at HSCLK=16MHz)
I2MnMOD register
t
CYC
t
HD:STA
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
Communication
speed
(I2MnMD1 and
I2MnMD0 bits)
Speed reduction
(I2MnDW1 and
I2MnDW0 bits)
00
(Standard
mode
: 100 kbps)
00 (no reduction)
160 φ
72 φ
88 φ
16 φ
72 φ
88 φ
72 φ
72 φ
88 φ
01 (10% reduction)
176 φ
80 φ
96 φ
16 φ
80 φ
96 φ
80 φ
80 φ
96 φ
10 (20% reduction)
192 φ
88 φ
104 φ
16 φ
88 φ
104 φ
88 φ
88 φ
104 φ
11 (30% reduction)
208 φ
96 φ
112 φ
16 φ
96 φ
112 φ
96 φ
96 φ
112 φ
01
(Fast
mode
: 400 kbps)
00 (no reduction)
40 φ
14 φ
26 φ
12 φ
14 φ
26 φ
14 φ
14 φ
26 φ
01 (10% reduction)
44 φ
16 φ
28 φ
12 φ
16 φ
28 φ
16 φ
16 φ
28 φ
10 (20% reduction)
48 φ
18 φ
30 φ
12 φ
18 φ
30 φ
18 φ
18 φ
30 φ
11 (30% reduction)
52 φ
20 φ
32 φ
12 φ
20 φ
32 φ
20 φ
20 φ
32 φ
10 or 11
(1 Mbps
mode
: 1 Mbps)
00 (no reduction)
16 φ
6 φ
10 φ
4 φ
6 φ
10 φ
6 φ
6 φ
10 φ
01 (10% reduction)
18 φ
7 φ
11 φ
4 φ
7 φ
11 φ
7 φ
7 φ
11 φ
10 (20% reduction)
19 φ
8 φ
11 φ
4 φ
8 φ
11 φ
7 φ
8 φ
11 φ
11 (30% reduction)
21 φ
9 φ
12 φ
4 φ
9 φ
12 φ
8 φ
9 φ
12 φ
The above clock counts are values when HSCLK is chosen for the operating frequency (I2MnCD1 and I2MnCD0
bits of the I2MnMOD register = "00"). When 1/2HSCLK is chosen, the counts increase in proportion to the
dividing ratio.
When using the high-speed clock for the I2C operation, specify the following I2C operating clock frequency
depending on the mode and the reference frequency of the PLL oscillation.
Standard mode: HSCLK or 1/2HSCLK
Fast mode:
HSCLK
1Mbps mode:
HSCLK
φ: Clock cycle of 1/mHSCLK
1/mHSCLK: Depends on settings for I2MnCD1 and I2MnCD0 bits of I2MnMOD register
(m=1, 2)
(Example)
HSCLK
= 16 MHz
: φ≈62.50 ns
= 8 MHz
: φ≈125.00 ns
[Note]
Ÿ
When the slave device uses the clock stretch function which holds the I2CMn_SCL pin at "L" level, the
time t
CYC
and time t
LOW
are extended.
Содержание ML62Q1000 Series
Страница 17: ...Chapter 1 Overview...
Страница 112: ...Chapter 2 CPU and Memory Space...
Страница 154: ...Chapter 3 Reset Function...
Страница 166: ...Chapter 4 Power Management...
Страница 196: ...Chapter 5 Interrupts...
Страница 248: ...Chapter 6 Clock generation Circuit...
Страница 274: ...Chapter 7 Low Speed Time Base Counter...
Страница 291: ...Chapter 8 16 Bit Timer...
Страница 320: ...Chapter 9 Functional Timer FTM...
Страница 382: ...Chapter 10 Watchdog Timer...
Страница 402: ...Chapter 11 Serial Communication Unit...
Страница 456: ...Chapter 12 I2 C Bus Unit...
Страница 491: ...Chapter 13 I2 C Master...
Страница 512: ...Chapter 14 DMA Controller...
Страница 531: ...Chapter 15 Buzzer...
Страница 550: ...Chapter 16 Simplified RTC...
Страница 559: ...Chapter 17 GPIO...
Страница 594: ...Chapter 18 External Interrupt Function...
Страница 612: ...Chapter 19 CRC Generator...
Страница 632: ...Chapter 20 Analog Comparator...
Страница 644: ...Chapter 21 D A Converter...
Страница 655: ...Chapter 22 Voltage Level Supervisor...
Страница 676: ...Chapter 23 Successive Approximation Type A D Converter...
Страница 709: ...Chapter 24 Regulator...
Страница 714: ...Chapter 25 Flash Memory...
Страница 743: ...Chapter 26 Code Option...
Страница 750: ...Chapter 27 LCD Driver...
Страница 788: ...Chapter 28 On Chip Debug Function...
Страница 795: ...Chapter 29 Safety Function...
Страница 813: ...Appendix A...
Страница 881: ...Revision History...