
ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000
5-8
5.2.4
Interrupt Enable Register 45 (IE45)
IE45 is a specific function register (SFR) to enable or disable the interrupt for each interrupt request.
The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
After the interrupt is accepted, the master interrupt enable flag (MIE) of the CPU is reset to "0", however, the applicable
each flag of IE01 is not reset and remains "1".
Address:
0xF024(IE4/IE45), 0xF025(IE5)
Access:
R/W
Access size:
8/16bit
Initial value:
0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Word
IE45
Byte
IE5
IE4
Bit
ETM5 ETM4
EFTM
5
EFTM
4
ECM
P1
ECM
P0
ESIU
21
ESIU
20
ETM3 ETM2
EFTM
3
EFTM
2
-
ESIU
11
ESIU
10
EI2C
U0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit No.
Bit symbol
name
Description
15
ETM5
This bit controls to enable or disable the 16bit Timer 5 interrupt (TM5INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
14
ETM4
This bit controls to enable or disable the 16bit Timer 4 interrupt (TM4INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
13
EFTM5
This bit controls to enable or disable the Functional Timer 5 interrupt (FTM5INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
12
EFTM4
This bit controls to enable or disable the Functional Timer 4 interrupt (FTM4INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
11
ECMP1
This bit controls to enable or disable the Analog Comparator 1 interrupt (CMP1INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
10
ECMP0
This bit controls to enable or disable the Analog Comparator 0 interrupt (CMP0INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
9
ESIU21
This bit controls to enable or disable the Serial Communication unit 21 interrupt (SIU21INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
8
ESIU20
This bit controls to enable or disable the Serial Communication unit 20 interrupt (SIU20INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
7
ETM3
This bit controls to enable or disable the 16bit Timer 3 interrupt (TM3INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
6
ETM2
This bit controls to enable or disable the 16bit Timer 2 interrupt (TM2INT).
0:
Disable the interrupt (initial value)
1:
Enable the interrupt
Содержание ML62Q1000 Series
Страница 17: ...Chapter 1 Overview...
Страница 112: ...Chapter 2 CPU and Memory Space...
Страница 154: ...Chapter 3 Reset Function...
Страница 166: ...Chapter 4 Power Management...
Страница 196: ...Chapter 5 Interrupts...
Страница 248: ...Chapter 6 Clock generation Circuit...
Страница 274: ...Chapter 7 Low Speed Time Base Counter...
Страница 291: ...Chapter 8 16 Bit Timer...
Страница 320: ...Chapter 9 Functional Timer FTM...
Страница 382: ...Chapter 10 Watchdog Timer...
Страница 402: ...Chapter 11 Serial Communication Unit...
Страница 456: ...Chapter 12 I2 C Bus Unit...
Страница 491: ...Chapter 13 I2 C Master...
Страница 512: ...Chapter 14 DMA Controller...
Страница 531: ...Chapter 15 Buzzer...
Страница 550: ...Chapter 16 Simplified RTC...
Страница 559: ...Chapter 17 GPIO...
Страница 594: ...Chapter 18 External Interrupt Function...
Страница 612: ...Chapter 19 CRC Generator...
Страница 632: ...Chapter 20 Analog Comparator...
Страница 644: ...Chapter 21 D A Converter...
Страница 655: ...Chapter 22 Voltage Level Supervisor...
Страница 676: ...Chapter 23 Successive Approximation Type A D Converter...
Страница 709: ...Chapter 24 Regulator...
Страница 714: ...Chapter 25 Flash Memory...
Страница 743: ...Chapter 26 Code Option...
Страница 750: ...Chapter 27 LCD Driver...
Страница 788: ...Chapter 28 On Chip Debug Function...
Страница 795: ...Chapter 29 Safety Function...
Страница 813: ...Appendix A...
Страница 881: ...Revision History...