LAPIS Semiconductor ML62Q1000 Series, Руководство пользователя, Страница: 489 / 882

ML62Q1000 Series User's Manual
Chapter 12 I2C Bus Unit
FEUL62Q1000 12-33
12.3.5 Operation Waveforms
Figure 12-11 shows the operation waveforms of I2CU0_SDA and I2CU0_SCL pins and the I2UM0BB flag of the
I2UM0STA register. Table 12-4 and 12-5 show the relationship between communication speeds and HSCLK clock
counts. Table 12-6 shows relationship between communication speeds and LSCLK clock counts.
Figure 12-11 Operation Waveforms of I2CU0_SDA and I2CU0_SCL Pins and I2UM0BB Flag
Table 12-4 Relationship between Communication Speeds and HSCLK Clock Counts (at HSCLK=24 MHz)
I2UM0MOD register
t
CYC
t
HD:STA
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
Communication
speed
(I2UM0MD1,
I2UM0MD0
bits)
Speed reduction
(I2UM0DW1,
I2UM0DW0 bits)
00
(Standard
mode
: 100 kbps)
00 (no reduction)
240 φ 108 φ 132 φ 24 φ 108 φ 132 φ 108 φ 108 φ 132 φ
01 (10% reduction)
264 φ 120 φ 144 φ 24 φ 120 φ 144 φ 120 φ 120 φ 144 φ
10 (20% reduction)
288 φ 132 φ 156 φ 24 φ 132 φ 156 φ 132 φ 132 φ 156 φ
11 (30% reduction)
312 φ 144 φ 168 φ 24 φ 144 φ 168 φ 144 φ 144 φ 168 φ
01
(Fast
mode
: 400 kbps)
00 (no reduction)
60 φ 24 φ 36 φ 12 φ 24 φ 36 φ 24 φ 24 φ 36 φ
01 (10% reduction)
66 φ 27 φ 39 φ 12 φ 27 φ 39 φ 27 φ 27 φ 39 φ
10 (20% reduction)
72 φ 30 φ 42 φ 12 φ 30 φ 42 φ 30 φ 30 φ 42 φ
11 (30% reduction)
78 φ 33 φ 45 φ 12 φ 33 φ 45 φ 33 φ 33 φ 45 φ
10 or 11
(1 Mbps
mode
: 1 Mbps)
00 (no reduction)
24 φ 10 φ 14 φ 4 φ 10 φ 14 φ 10 φ 10 φ 14 φ
01 (10% reduction)
26 φ 11 φ
15
φ 4 φ 11 φ 15 φ 11 φ 11 φ 15 φ
10 (20% reduction)
29 φ 13 φ 16 φ 4 φ 13 φ 16 φ 12 φ 13 φ 16 φ
11 (30% reduction)
31 φ 14 φ 17 φ 4 φ 14 φ 17 φ 13 φ 14 φ 17 φ
The above clock counts are values when HSCLK is chosen for the operating frequency (I2UM0CD2 to 0 bits of
the I2UM0MOD register = "000"). When 1/2 or 1/4HSCLK is chosen, the counts increase in proportion to the
dividing ratio.
When using the high-speed clock for the I2C operation, specify the following I2C operating clock frequency
depending on the mode and the reference frequency of the PLL oscillation.
Standard mode: HSCLK to 1/4HSCLK
Fast mode: HSCLK to 1/2HSCLK
1Mbps mode: HSCLK to 1/2HSCLK
φ: Clock cycle of 1/mHSCLK
1/mHSCLK: Set in I2UM0CD2 to I2UM0CD0 bits of the I2UM0MOD register.
(m=1, 2, 4)
(Example)
HSCLK = 24 MHz
: φ≈41.67 ns
= 12 MHz
: φ≈83.33 ns
= 6 MHz
: φ≈166.67 ns
I2CU0_SDA pin
Start
condition
Restart
condition
Stop
condition
I2CU0 SCL pin
t
HD:STA
t
LOW
t
HIGH
t
HD:DAT
t
SU:STA
t
SU:STO
t
BUF
t
SU:DAT
I2UM0BB bit
t
CYC