
ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000
5-41
5.3.4 Notes on Interrupt Routine (with Interrupt Level Control Disabled)
Writing "0" to the ILE bit of the interrupt level control enable register (ILEN) causes the interrupt level control to be
disabled.
The description below shows notes on each of the following states when the interrupt level control is not in use.
Ÿ
When the sub routine is called/not called in the interrupt routine while execution of the maskable interrupt is in
progress (state A).
Ÿ
When the sub routine is called/not called in the interrupt routine while execution of a non-maskable interrupt is in
progress (state B).
State A: Maskable interrupt is being executed
A-1: When a subroutine is not called in an interrupt routine
A-1-1: When multiple interrupts are disabled
• When the script is written in the assembly language
• Processing immediately after the start of interrupt routine execution
No specific notes.
• Processing at the end of interrupt routine execution
Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register
to PSW.
• When the script is written in C
Define the interrupt routine using the INTERRUPT pragma. Specify "1" in the category field. In this way,
appropriate codes are produced through the C compiler (CCU8).
Example of description: State A-1-1
For assembly language:
Intrpt_A-1-1;
; State of A-1-1
DI
; Disable interrupt
:
:
:
RTI
; Return PC from ELR
; Return PSW form EPSW
; End of interrupt routine
For C language:
static void Intrpt_A_1_1(void);
#pragma interrupt Intrpt_A_1_1 0x10 1
static void Intrpt_A_1_1(void)
{
_DI();
/* Disable interrupt */
:
}
/* End of interrupt routine */
Содержание ML62Q1000 Series
Страница 17: ...Chapter 1 Overview...
Страница 112: ...Chapter 2 CPU and Memory Space...
Страница 154: ...Chapter 3 Reset Function...
Страница 166: ...Chapter 4 Power Management...
Страница 196: ...Chapter 5 Interrupts...
Страница 248: ...Chapter 6 Clock generation Circuit...
Страница 274: ...Chapter 7 Low Speed Time Base Counter...
Страница 291: ...Chapter 8 16 Bit Timer...
Страница 320: ...Chapter 9 Functional Timer FTM...
Страница 382: ...Chapter 10 Watchdog Timer...
Страница 402: ...Chapter 11 Serial Communication Unit...
Страница 456: ...Chapter 12 I2 C Bus Unit...
Страница 491: ...Chapter 13 I2 C Master...
Страница 512: ...Chapter 14 DMA Controller...
Страница 531: ...Chapter 15 Buzzer...
Страница 550: ...Chapter 16 Simplified RTC...
Страница 559: ...Chapter 17 GPIO...
Страница 594: ...Chapter 18 External Interrupt Function...
Страница 612: ...Chapter 19 CRC Generator...
Страница 632: ...Chapter 20 Analog Comparator...
Страница 644: ...Chapter 21 D A Converter...
Страница 655: ...Chapter 22 Voltage Level Supervisor...
Страница 676: ...Chapter 23 Successive Approximation Type A D Converter...
Страница 709: ...Chapter 24 Regulator...
Страница 714: ...Chapter 25 Flash Memory...
Страница 743: ...Chapter 26 Code Option...
Страница 750: ...Chapter 27 LCD Driver...
Страница 788: ...Chapter 28 On Chip Debug Function...
Страница 795: ...Chapter 29 Safety Function...
Страница 813: ...Appendix A...
Страница 881: ...Revision History...