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ML62Q1000 Series User's Manual
Chapter 11 Serial Communication Unit
FEUL62Q1000 11-52
11.3.2.8 Detection of Start Bit
The start bit is sampled with the baud rate generator base clock. Therefore, the start bit detection may be delayed for one
cycle of the baud rate generator clock at the maximum.
Figure 11-17 shows the start bit detection timing.
Figure 11-17 Start Bit Detection Timing (with Positive Logic)
11.3.2.9 Sampling Timing
When the start bit is detected, the received data that was input to SUn_RXDn is sampled almost at the center of the baud
rate, then loaded to the shift register.
This sampling timing the shift register uses to load data can be adjusted for one clock of the baud rate generator clock in
the Un0RSS bit of the UARTn mode register 0 (UAn0MODL).
Figure 11-18 shows the relationship between the Un0RSS bit and the sampling timing.
(1) When the baud rate generator count value is "7" (odd)
(2) When the baud rate generator count value is "8" (even)
Figure 11-18 Relationship between Un0RSS Bit and Sampling Timing
Sampling by baud rate
generator clock
SUn_RXDn
Maximum one-cycle delay
Start bit
Baud rate generator clock
SUn_RXDn
0 3 2 6 0 3 2 6
Sampling timing
Un0RSS=1 Un0RSS=0
Count value = 7
Baud rate generator clock
RXD
0 3 2 7 0 3 2 7
Sampling timing
Un0RSS=1 Un0RSS=0
Count value = 8