GE
RAFT
V
OLUSON
™ P8 / V
OLUSON
™ P6
DIRECTION 5723243, R
EVISION
6
DRAFT (M
AY
23, 2018)
B
ASIC
S
ERVICE
M
ANUAL
5-26
Section 5-3 - FrontEnd Processor
5-3-3-1
DRFM - FPGA
A.) Beamformer interface
•
LVDS-interface
•
Raw ultrasound data is transferred from the Beamformer to the Interface FPGA.
•
Configuration data (Probe Setup data, Beam Setup data) is transferred from the Interface FPGA to
the Beamformer.
•
FPGA configuration data is transferred from the Interface FPGA to the Beamformer
B.) DMA Logic
•
Receives pre-processed ultrasound data coming from the Processing FPGA.
•
Stores this data in the Line Memory buffer (2x SDRAM)
•
Transfers buffered data by DMA-transfer via PCI and PCI-Express to the PC
-
Non-TimeMotion data (B, C): DMA0
-
TimeMotion data (M, PW): DMA1.
C.) T-DPI FPGA programming interface
•
This FPGA is the interface between the System connectors and the DRFM.
D.) Ultrasound Data Pre-processing
•
Raw ultrasound data is coming in from the Interface FPGA. It is pre-processed.Further processing
will be done by the PC. The pre-processed data is transferred back to the Interface-FPGA.
E.) System control
•
PRF (Pulse Repetition Frequency) Generator
•
Line Number (Lateral Position)
•
Control of TX-Power DACs (generation of TX POWER reference voltage)
•
Controls discharge of capacity on DPS board during the reduction of TX POWER
•
Shut-down signal coming from the DBM64 board is passed to the SOM
•
Probe Select signals, which indicate that a probe is connected to a probe connector.
•
Probe Code Interface: The Probe Code can be read from a connected probe, or a new code can be
written into the probe..
•
Audio Control:
-
PW Doppler Audio Output for buffered signals from the PC
F.) 4D motor control
•
Master of Control for 3D-Sweep
•
Master of Control for 4D-Sweeps
•
Generation of Volume Trigger and Frame Trigger (for 4D)
•
Drives motor (in 3D/4D-probes) via SIN (sine-signal) & COS (cosine signal)
•
The HALL-signal coming from the 3D/4D probe is passed to the DSP for zero position detection.
