Operation Modes
10-38
ADSP-214xx SHARC Processor Hardware Reference
for every frame, and therefore emulates I
2
S mode. So it is a hybrid
between multichannel and I
2
S mode.
Clocking Options
In packed mode, the serial ports can either accept an external serial clock
or generate it internally. The
ICLK
bit in the
SPCTL
register determines the
selection of these options. For internally-generated serial clocks, the
CLK-
DIV
bits in the
DIVx
register configure the serial clock rate. Finally,
programs can select whether the serial clock edge is used for sampling or
driving serial data and/or frame syncs. This selection is performed using
the
CKRE
bit in the
SPCTL
register.
Frame Sync Options
The frame sync period in packed mode is defined as:
FS period =
SLEN
× number of channels.
The frame sync can be configured in master or slave mode depending on
the
IMFS
bit. Moreover the logic level can be changed with the
LMFS
bit.
Figure 10-9. Packed Mode 128 Operation
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
BLANK SLOT
4 SCLK
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BLANK SLOT
4 SCLK
DATA
20-BIT DATA
16-BIT DATA
BCLK
BCLK
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–1
MSB
–2
MSB
–3
MSB
–4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
LSB
LSB
MSB
L/
R
CLK
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Содержание SHARC ADSP-214 Series
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Страница 72: ...Notation Conventions lxxii ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 130: ...Programming Model 2 52 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 264: ...Programming Models 3 134 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
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Страница 396: ...Effect Latency 7 28 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
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Страница 616: ...Debug Features 14 22 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
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Страница 1132: ...Register Listing A 306 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 1192: ...Index I 34 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...