Analog Devices SHARC ADSP-214 Series, Справочник по аппаратуре

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ADSP-214xx SHARC Processor Hardware Reference 3-119
External Port
external DDR2 memory. The throughput numbers shown are measured
by running a loop of 1024 read/writes (512 in case of SIMD reads/writes).
For the analysis, 16-bit DDR2 is used (t
FAW
=10, t
RRD
=2, t
RTP
=2,
t
MRD
=3, t
RCD
=3, t
WTR
=1, t
RP
=3, t
RAS
=8, CL=4, AL=4, t
WR
=4).
Throughput is calculated from start of the first iteration of the loop to the
end of the last iteration of the loop.
External Instruction Fetch Throughput
The actual throughput execution from external SDRAM is dependent on
the configuration of the SDRAM. The SDRAM can be programmed to
run at a number of different frequency ratios with respect to the core
clock, the fastest being half of the core clock (or the same as the peripheral
clock). The core and SDRAM controller have been enhanced so that
throughput is maximized when SDRAM is programmed to run at half the
core clock frequency and the instructions being fetched are sequential.

Read optimization logic does not apply to external code execution.
Table 3-32. Core Throughput, 400 MHz Core Clock
Operation DDR2 Clock Clock Ratio Throughput
Core Reads (SISD/SIMD)
133 MHz 1:3 495M bytes/sec.
200 MHz 1:2 742M bytes/sec.
Core Writes (SISD)
133 MHz 1:3 529M bytes/sec.
200 MHz 1:2 793M bytes/sec.
Core Writes (SIMD)
133 MHz 1:3 531M bytes/sec.
200 MHz 1:2 796M bytes/sec.
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