ADSP-214xx SHARC Processor Hardware Reference
8-15
Media Local Bus
Interrupt Source
One interrupt is shared by the system status and channel status interrupts.
Servicing Interrupts
System status interrupts interrupts are generated on events that allow sys-
tem software to monitor and control the status of the MediaLB Network.
These interrupts can be unmasked by clearing the corresponding bit in
MLB_SMCR
register. The interrupt is cleared within the ISR before the RTI
instruction by writing one to corresponding bit in the
MLB_SSCR
register.
Channel status interrupts are generated on events corresponding to a par-
ticular logical channel (0–31). These interrupts can be unmasked by
clearing the appropriate bits (16–23) in the
MLB_CECRx
register.
The channel interrupt status register (
MLB_CICR
) reflects the interrupt sta-
tus of the individual logical channels. For example, if an interrupt is
pending in logical channel 0, the corresponding bit (bit 0) is set in the
MLB_CICR
register. These bits are set by hardware when a channel interrupt
is generated. The channel interrupt bits are sticky and can only be reset by
software. To clear a particular bit in the
MLB_CICR
register, software must
clear all of the unmasked status bits in the corresponding
MLB_CSCRn
regis-
ters. Therefore, if bit 0 of the
MLB_CICR
register is set, writing 0xFFFF to
MLB_CSCR
bit 0 register clears
MLB_CICR
bit 0. This step must be included
the channel interrupt ISR before the RTI instruction to ensure that the
interrupt is not regenerated.
Debug Features
The following sections provide information to assist in MediaLB debug.
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Содержание SHARC ADSP-214 Series
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Страница 616: ...Debug Features 14 22 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
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Страница 1132: ...Register Listing A 306 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...
Страница 1192: ...Index I 34 ADSP 214xx SHARC Processor Hardware Reference www BDTIC com ADI...