ABB Relion 670 series, Техническое руководство

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The synchronization of the hardware clock to the software clock is necessary only when GPS or
IRIG B 00X with optical fiber, IEEE 1344 is used for differential protection. The two clock systems
are synchronized by a special clock synchronization unit with two modes, fast and slow. A special
feature, an automatic fast clock time regulator is used. The automatic fast mode makes the
synchronization time as short as possible during pickup or at interruptions/disturbances in the
GPS timing. The fast and slow settings are also available on the local HMI.
The hardware and software clocks are not synchronized if a GPS clock is used.
Fast clock synchronization mode
At start-up and after interruptions in the GPS or IRIG B time signals, the deviation between the
GPS time and the internal differential time system can be substantial. A new start-up is also
required, for example, after maintenance of the auxiliary voltage system.
When the time difference is >16μs, the differential function is blocked and the time regulator for
the hardware clock automatically uses a fast mode to synchronize the clock systems. The time
adjustment is made with an exponential function, that is, with big time adjustment steps in the
beginning, and then smaller steps until a time deviation between the GPS time and the differential
time system of <16μs has been reached. The differential function is then enabled and the
synchronization remains in fast mode or switches to slow mode depending on the setting.
Slow clock synchronization mode
During normal service, a setting with slow synchronization mode is used. This prevents the
hardware clock to make too big time steps, >16µs, emanating from the differential protection
requirement of correct timing.
Synchronization principle
M11346-83 v4
From a general point of view synchronization can be seen as a hierarchical structure. A function is
synchronized from a higher level and provides synchronization to lower levels.
Function
Synchronization from
a higher level
Optional synchronization of
modules at a lower level
IEC09000342-1-en.vsd
IEC09000342 V1 EN-US
Figure 630: Synchronization principle
A function is said to be synchronized when it periodically receives synchronization messages from
a higher level. As the level decreases, the accuracy of the synchronization decreases as well. A
function can have several potential sources of synchronization, with different maximum errors.
This gives the function the possibility to choose the source with the best quality, and to adjust its
internal clock based on this source. The maximum error of a clock can be defined as:
Section 21 1MRK 502 066-UUS B
Basic IED functions
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Technical manual