Xilinx LogiCORE IP, Product Manual

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XAUI v12.3 Product Guide www.xilinx.com 68
PG053 April 6, 2016
Chapter 2: Product Specification
Table 2-52 shows the 10G PHY XGXS Lane register bit definitions.
MDIO Register 4.25: 10G PHY XGXS Test Control
Figure 2-37 shows the MDIO Register 4.25: 10G XGXS Test Control.
Table 2-53 shows the 10G PHY XGXS Test Control register bit definitions.
Table 2 ‐ 52: 10G PHY XGXS Lane Status Register Bit Definitions
Bit Name Description Attributes Default Value
4.24.15:13 Reserved The block always returns 0 for these bits. R/O All 0s
4.24.12
PHY XGXS
Lane
Alignment
Status
1 = PHY XGXS receive lanes aligned;
0 = PHY XGXS receive lanes not aligned.
RO -
4.24.11
Pattern Testing
Ability
The block always returns 1 for this bit. R/O 1
4.24.10:4 Reserved The block always returns 0 for these bits. R/O All 0s
4.24.3 Lane 3 Sync
1 = Lane 3 is synchronized;
0 = Lane 3 is not synchronized.
R/O -
4.24.2 Lane 2 Sync
1 = Lane 2 is synchronized;
0 = Lane 2 is not synchronized.
R/O -
4.24.1 Lane 1 Sync
1 = Lane 1 is synchronized;
0 = Lane 1 is not synchronized.
R/O -
4.24.0 Lane 0 Sync
1 = Lane 0 is synchronized;
0 = Lane 0 is not synchronized.
R/O -
X-Ref Target - Figure 2-37
Figure 2 ‐ 37: 10G PHY XGXS Test Control Register
RSVD TEST
P
A
TTERN ENABLE
TEST
P
A
TTERN SELECT
15 3 2 1 0
Reg 4.25
X13709
Table 2 ‐ 53: 10G PHY XGXS Test Control Register Bit Definitions
Bit Name Description Attributes Default Value
4.25.15:3 Reserved The block always returns 0 for these bits. R/O All 0s
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