Xilinx LogiCORE IP, Product Manual, Page: 33 / 142

XAUI v12.3 Product Guide www.xilinx.com 33
PG053 April 6, 2016
Chapter 2: Product Specification
Table 2-12 shows the ports that are associated with system clocks and resets.
Table 2-13 shows the ports that are associated with system clocks and resets.
Table 2 ‐ 12: Clock and Reset Ports with Shared Logic in the Example Design
Signal Name Direction Description
dclk in
Clock used as the DRP clock, and also as a stable reference clock for the
detection of the feedback and reference clock signals to the QPLL. The
input reference clock to the QPLL or any output clock generated from
the QPLL (for example, TXOUTCLK) must not be used to drive this clock.
For UltraScale devices, this clock is also used in the internal state
machines for the configuration of the transceiver.
refclk_p/refclk_n in
Transceiver differential reference clock to the core when shared logic is
included in the core.
refclk in
Transceiver reference clock to the core when shared logic is included in
the example design.
clk156_out out
System clock for the encrypted HDL logic and for the device-specific
transceiver logic ports. This clock must have a frequency of 156.25 MHz
for 10G XAUI operation. 312.5 MHz for 20G XAUI operation.
clk156_lock out
This active-High PLL frequency lock signal indicates that the PLL
frequency is within predetermined tolerance. The transceiver and its
clock outputs are not reliable until this condition is met.
reset in Asynchronous external reset
Table 2 ‐ 13: Clock and Reset Ports with Shared Logic in Core
Signal Name Direction Description
dclk in
Clock used as the DRP clock, and also as a stable reference clock for the
detection of the feedback and reference clock signals to the QPLL. The
input reference clock to the QPLL or any output clock generated from
the QPLL (for example, TXOUTCLK) must not be used to drive this clock.
For UltraScale devices this clock is also used in the internal state
machines for the configuration of the transceiver.
refclk_p in Differential transceiver reference clock “p.”
refclk_n in Differential transceiver reference clock “n.”
clk156_out out
System clock for the encrypted HDL logic and for the device-specific
transceiver logic ports. This clock must have a frequency of 156.25 MHz
for 10G XAUI operation. 312.5 MHz for 20G XAUI operation.
clk156_lock out
This active-High PLL frequency lock signal indicates that the PLL
frequency is within predetermined tolerance. The transceiver and its
clock outputs are not reliable until this condition is met.
reset in Asynchronous external reset
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