XAUI v12.3 Product Guide
30
PG053 April 6, 2016
Chapter 2:
Product Specification
gt_txresetdone[3:0]
out
clk156_out
When asserted the serial transceiver TX has finished reset
and is ready for use.
RX Reset and Initialization
gt_rxpmareset[3:0]
in
Async
Starts the RX PMA reset process.
gt_rxpcsreset[3:0]
in
Async
Starts the RX PCS reset process.
gt_rxpmaresetdone[3:0]
out
Async
gt_rxresetdone[3:0]
out
clk156_out
When asserted the serial transceiver RX has finished reset
and is ready for use.
Clocking
gt_rxbufstatus[11:0]
out
clk156_out
RX buffer status.
gt_txphaligndone[3:0]
out
Async
TX phase alignment done.
gt_txphinitdone[3:0]
out
Async
TX phase alignment initialization done.
gt_txdlysresetdone[3:0]
out
Async
TX delay alignment soft reset done.
gt_qplllock
out
Async
This active-High PLL frequency lock signal indicates that the
PLL frequency is within predetermined tolerance.
Signal Integrity and Functionality
Eye Scan
gt_eyescantrigger[3:0]
in
clk156_out
Causes a trigger event.
gt_eyescanreset[3:0]
in
Async
This port is driven High and then deasserted to start the
EYESCAN reset process.
gt_eyescandataerror[3:0] out
Async
Asserts High for one rec_clk cycle when an (unmasked) error
occurs while in the COUNT or ARMED state.
gt_rxrate[11:0]
in
clk156_out
This port dynamically controls the setting for the RX serial
clock divider.
Loopback
gt_loopback[11:0]
in
Async
Determines the loopback mode.
Polarity
gt_rxpolarity[3:0]
in
clk156_out
The rxpolarity port can invert the polarity of incoming data.
gt_txpolarity[3:0]
in
clk156_out
The txpolarity port can invert the polarity of outgoing data.
RX Decision Feedback Equalizer (DFE)
gt_rxlpmen[3:0]
in
Async
RX datapath.
0: DFE.
1: LPM.
gt_rxdfelpmreset[3:0]
in
Async
Reset for LPM and DFE datapath.
TX Driver
gt_txpostcursor[19:0]
in
Async
Transmitter post-cursor TX post-emphasis control.
Table 2
‐
9:
Transceiver Control and Status Ports — UltraScale Architectures
(Cont’d)
Signal Name
Direction
Clock
Domain
Description
