XAUI v12.3 Product Guide
29
PG053 April 6, 2016
Chapter 2:
Product Specification
gt1_drpwe
in
dclk
DRP write enable for channel 1.
0: Read operation when drpen is 1.
1: Write operation when drpen is 1.
GT2 DRP
gt2_drpaddr[8:0]
in
dclk
DRP address bus for channel 2
gt2_drpen
in
dclk
DRP enable signal.
0: No read or write operation performed.
1: enables a read or write operation.
gt2_drpdi[15:0]
in
dclk
Data bus for writing configuration data to the transceiver
for channel 2.
gt2_drpdo[15:0]
out
dclk
Data bus for reading configuration data from the
transceiver for channel 2.
gt2_drprdy
out
dclk
Indicates operation is complete for write operations and
data is valid for read operations for channel 2.
gt2_drpwe
in
dclk
DRP write enable for channel 2.
0: Read operation when drpen is 1.
1: Write operation when drpen is 1.
GT3 DRP
gt3_drpaddr[8:0]
in
dclk
DRP address bus for channel 3
gt3_drpen
in
dclk
DRP enable signal.
0: No read or write operation performed.
1: enables a read or write operation.
gt3_drpdi[15:0]
in
dclk
Data bus for writing configuration data to the transceiver
for channel 3.
gt3_drpdo[15:0]
out
dclk
Data bus for reading configuration data from the
transceiver for channel 3.
gt3_drprdy
out
dclk
Indicates operation is complete for write operations and
data is valid for read operations for channel 3.
gt3_drpwe
in
dclk
DRP write enable for channel 3.
0: Read operation when drpen is 1.
1: Write operation when drpen is 1.
DRP Reset
gt_pcsrsvdin[63:0] in
Async
Bits 2, 18, 34 and 50 are connected to port pcsrsvdin[2] of
GT lanes 0, 1, 2 and 3 respectively. See the appropriate
transceiver user guide for more details.
TX Reset and Initialization
gt_txpmareset[3:0]
in
Async
Starts the TX PMA reset process.
gt_txpcsreset[3:0]
in
Async
Starts the TX PCS reset process.
Table 2
‐
9:
Transceiver Control and Status Ports — UltraScale Architectures
(Cont’d)
Signal Name
Direction
Clock
Domain
Description
