XAUI v12.3 Product Guide
28
PG053 April 6, 2016
Chapter 2:
Product Specification
GT3 Status
gt3_rxdisperr_out[3:0]
out
clk156_out Active-High indicates the corresponding byte of the
received data has a disparity error
gt3_rxnotintable_out[3:0]
out
clk156_out
Active-High indicates the corresponding byte of the
received data was not a valid character in the 8B/10B
table.
gt3_rxcommadet_out
out
clk156_out This signal is asserted when the comma alignment
block detects a comma.
Table 2
‐
8:
Transceiver Control and Status Ports —7 Series FPGAs
(Cont’d)
Signal Name
Direction
Clock
Domain
Description
Table 2
‐
9:
Transceiver Control and Status Ports — UltraScale Architectures
Signal Name
Direction
Clock
Domain
Description
GT0 DRP
gt0_drpaddr[8:0]
in
dclk
DRP address bus for channel 0
gt0_drpen
in
dclk
DRP enable signal.
0: No read or write operation performed.
1: enables a read or write operation.
gt0_drpdi[15:0]
in
dclk
Data bus for writing configuration data to the transceiver
for channel 0.
gt0_drpdo[15:0]
out
dclk
Data bus for reading configuration data from the
transceiver for channel 0.
gt0_drprdy
out
dclk
Indicates operation is complete for write operations and
data is valid for read operations for channel 0.
gt0_drpwe
in
dclk
DRP write enable for channel 0.
0: Read operation when drpen is 1.
1: Write operation when drpen is 1.
GT1 DRP
gt1_drpaddr[8:0]
in
dclk
DRP address bus for channel 1
gt1_drpen
in
dclk
DRP enable signal.
0: No read or write operation performed.
1: enables a read or write operation.
gt1_drpdi[15:0]
in
dclk
Data bus for writing configuration data to the transceiver
for channel 1.
gt1_drpdo[15:0]
out
dclk
Data bus for reading configuration data from the
transceiver for channel 1.
gt1_drprdy
out
dclk
Indicates operation is complete for write operations and
data is valid for read operations for channel 1.
