Xilinx LogiCORE IP, Product Manual

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XAUI v12.3 Product Guide www.xilinx.com 64
PG053 April 6, 2016
Chapter 2: Product Specification
Table 2-47 shows the PHY XS Devices Identifier registers bit definitions.
MDIO Register 4.4: PHY XS Speed Ability
Figure 2-32 shows the MDIO Register 4.4: PHY XS Speed Ability.
Table 2-48 shows the PHY XS Speed Ability register bit definitions.
Table 2 ‐ 47: PHY XS Device Identifier Registers Bit Definitions
Bit Name Description Attributes
Default
Value
4.2.15:0
PHY XS
Identifier
The block always returns 0 for these bits and
ignores writes.
R/O All 0s
4.3.15:0
PHY XS
Identifier
The block always returns 0 for these bits and
ignores writes.
R/O All 0s
X-Ref Target - Figure 2-32
Figure 2 ‐ 32: PHY XS Speed Ability Register
RSVD 10G CAP
ABLE
15 0
Reg 4.4
X13704
Table 2 ‐ 48: PHY XS Speed Ability Register Bit Definitions
Bit Name Description Attribute Default Value
4.4.15:1 Reserved
The block always returns 0 for these bits and
ignores writes.
R/O All 0s
4.4.0 10G Capable
The block always returns 1 for this bit and
ignores writes.
R/O 1
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